4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
36 * \author Daniele Basile <asterix@develer.com>
38 * AT91SAM7 register definitions.
39 * This file is based on NUT/OS implementation. See license below.
43 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
45 * Redistribution and use in source and binary forms, with or without
46 * modification, are permitted provided that the following conditions
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71 * For additional information see http://www.ethernut.de/
77 #include <cfg/compiler.h>
79 #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7S256
80 #define FLASH_BASE 0x100000UL
81 #define RAM_BASE 0x200000UL
83 #define TC_BASE 0xFFFA0000 ///< Timer/counter base address.
84 #define UDP_BASE 0xFFFB0000 ///< USB device port base address.
85 #define TWI_BASE 0xFFFB8000 ///< Two-wire interface base address.
86 #define USART0_BASE 0xFFFC0000 ///< USART 0 base address.
87 #define USART1_BASE 0xFFFC4000 ///< USART 1 base address.
88 #define PWMC_BASE 0xFFFCC000 ///< PWM controller base address.
89 #define SSC_BASE 0xFFFD4000 ///< Serial synchronous controller base address.
90 #define ADC_BASE 0xFFFD8000 ///< ADC base address.
92 #define AIC_BASE 0xFFFFF000 ///< AIC base address.
93 #define DBGU_BASE 0xFFFFF200 ///< DBGU base address.
94 #define PIOA_BASE 0xFFFFF400 ///< PIO A base address.
95 #define PMC_BASE 0xFFFFFC00 ///< PMC base address.
96 #define RSTC_BASE 0xFFFFFD00 ///< Resect controller register base address.
97 #define RTT_BASE 0xFFFFFD20 ///< Realtime timer base address.
98 #define PIT_BASE 0xFFFFFD30 ///< Periodic interval timer base address.
99 #define WDT_BASE 0xFFFFFD40 ///< Watch Dog register base address.
100 #define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address.
101 #define MC_BASE 0xFFFFFF00 ///< Memory controller base.
103 #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
104 #define CAN_BASE 0xFFFD0000 ///< PWM controller base address.
105 #define EMAC_BASE 0xFFFDC000 ///< Ethernet MAC address.
106 #define SPI0_BASE 0xFFFE0000 ///< SPI0 base address.
107 #define SPI1_BASE 0xFFFE4000 ///< SPI1 base address.
108 #define PIOB_BASE 0xFFFFF600 ///< PIO base address.
111 #if CPU_ARM_AT91SAM7S256
112 #define SPI_BASE 0xFFFE0000 ///< SPI0 base address.
115 #define PIO_HAS_MULTIDRIVER 1
116 #define PIO_HAS_PULLUP 1
117 #define PIO_HAS_PERIPHERALSELECT 1
118 #define PIO_HAS_OUTPUTWRITEENABLE 1
120 #define DBGU_HAS_PDC 1
121 #define SPI_HAS_PDC 1
122 #define SSC_HAS_PDC 1
123 #define USART_HAS_PDC 1
126 #error No base addrese register definition for selected ARM CPU
130 #include "at91_aic.h"
131 #include "at91_pit.h"
132 #include "at91_pmc.h"
134 #include "at91_wdt.h"
135 #include "at91_rstc.h"
136 #include "at91_pio.h"
138 #include "at91_dbgu.h"
140 #include "at91_pwm.h"
141 #include "at91_spi.h"
142 #include "at91_twi.h"
143 //TODO: add other peripherals
146 * Peripheral Identifiers and Interrupts
149 #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X128
150 #define FIQ_ID 0 ///< Fast interrupt ID.
151 #define SYSC_ID 1 ///< System controller interrupt.
152 #define US0_ID 6 ///< USART 0 ID.
153 #define US1_ID 7 ///< USART 1 ID.
154 #define SSC_ID 8 ///< Synchronous serial controller ID.
155 #define TWI_ID 9 ///< Two-wire interface ID.
156 #define PWMC_ID 10 ///< PWM controller ID.
157 #define UDP_ID 11 ///< USB device port ID.
158 #define TC0_ID 12 ///< Timer 0 ID.
159 #define TC1_ID 13 ///< Timer 1 ID.
160 #define TC2_ID 14 ///< Timer 2 ID.
162 #define IRQ0_ID 30 ///< External interrupt 0 ID.
163 #define IRQ1_ID 31 ///< External interrupt 1 ID.
165 #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
166 #define PIOA_ID 2 ///< Parallel A I/O controller ID.
167 #define PIOB_ID 3 ///< Parallel B I/O controller ID.
168 #define SPI0_ID 4 ///< Serial peripheral interface 0 ID.
169 #define SPI1_ID 5 ///< Serial peripheral interface 1 ID.
170 #define CAN_ID 15 ///< CAN controller ID.
171 #define EMAC_ID 16 ///< Ethernet MAC ID.
172 #define ADC_ID 17 ///< Analog to digital converter ID.
177 #if CPU_ARM_AT91SAM7S256
178 #define PIOA_ID 2 ///< Parallel I/O controller ID.
179 /* ID 3 is reserved */
180 #define ADC_ID 4 ///< Analog to digital converter ID.
181 #define SPI_ID 5 ///< Serial peripheral interface ID.
182 #define SPI0_ID SPI_ID ///< Alias
186 #error No peripheral ID and interrupts definition for selected ARM CPU
192 * USART & DEBUG pin names
195 #if CPU_ARM_AT91SAM7S256
202 #elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
203 #define RXD0 0 // PA0
204 #define TXD0 1 // PA1
205 #define RXD1 5 // PA5
206 #define TXD1 6 // PA6
207 #define DTXD 28 // PA28
208 #define DRXD 27 // PA27
210 #error No USART & debug pin names definition for selected ARM CPU
218 #if CPU_ARM_AT91SAM7S256
219 #define SPI0_NPCS0 11 // Same as NSS pin.
224 #elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
225 #define SPI0_NPCS0 12 // Same as NSS pin. PA12
226 #define SPI0_NPCS1 13 // PA13
227 #define SPI0_NPCS2 14 // PA14
228 #define SPI0_NPCS3 15 // PA15
229 #define SPI0_MISO 16 // PA16
230 #define SPI0_MOSI 17 // PA17
231 #define SPI0_SPCK 18 // PA18
233 #define SPI1_NPCS0 21 // Same as NSS pin. PA21
234 #define SPI1_NPCS1 25 // PA25
235 #define SPI1_NPCS2 26 // PA26
236 #define SPI1_NPCS3 29 // PA29
237 #define SPI1_MISO 24 // PA24
238 #define SPI1_MOSI 23 // PA23
239 #define SPI1_SPCK 22 // PA22
242 #error No SPI pins name definition for selected ARM CPU
248 * Timer counter pins definition.
251 #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
252 #define TIOA0 23 // PB23
253 #define TIOB0 24 // PB24
254 #define TIOA1 25 // PB25
255 #define TIOB1 26 // PB26
256 #define TIOA2 27 // PB27
257 #define TIOB2 28 // PB28
260 #error No Timer Conter pin names definition for selected ARM CPU
266 * PWM pins definition.
269 #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
270 #define TIOA0 23 // PB23
271 #define TIOB0 24 // PB24
272 #define TIOA1 25 // PB25
273 #define TIOB1 26 // PB26
274 #define TIOA2 27 // PB27
275 #define TIOB2 28 // PB28
278 #error No Timer Conter pin names definition for selected ARM CPU
284 * TWI pins definition.
287 #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
291 #error No TWI pin names definition for selected ARM CPU
294 #endif /* AT91SAM7_H */