4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
37 * AT91SAM7S256 register definitions.
38 * This file is based on NUT/OS implementation. See license below.
42 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
48 * 1. Redistributions of source code must retain the above copyright
49 * notice, this list of conditions and the following disclaimer.
50 * 2. Redistributions in binary form must reproduce the above copyright
51 * notice, this list of conditions and the following disclaimer in the
52 * documentation and/or other materials provided with the distribution.
53 * 3. Neither the name of the copyright holders nor the names of
54 * contributors may be used to endorse or promote products derived
55 * from this software without specific prior written permission.
57 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
60 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
61 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
63 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
64 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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70 * For additional information see http://www.ethernut.de/
73 #ifndef AT91SAM7S256_H
74 #define AT91SAM7S256_H
76 #include <cfg/compiler.h>
78 #define FLASH_BASE 0x100000UL
79 #define RAM_BASE 0x200000UL
81 #define TC_BASE 0xFFFA0000 ///< Timer/counter base address.
82 #define UDP_BASE 0xFFFB0000 ///< USB device port base address.
83 #define TWI_BASE 0xFFFB8000 ///< Two-wire interface base address.
84 #define USART0_BASE 0xFFFC0000 ///< USART 0 base address.
85 #define USART1_BASE 0xFFFC4000 ///< USART 1 base address.
86 #define PWMC_BASE 0xFFFCC000 ///< PWM controller base address.
87 #define SSC_BASE 0xFFFD4000 ///< Serial synchronous controller base address.
88 #define ADC_BASE 0xFFFD8000 ///< ADC base address.
89 #define SPI_BASE 0xFFFE0000 ///< SPI0 base address.
91 #define AIC_BASE 0xFFFFF000 ///< AIC base address.
92 #define DBGU_BASE 0xFFFFF200 ///< DBGU base address.
93 #define PIOA_BASE 0xFFFFF400 ///< PIO A base address.
94 #define PMC_BASE 0xFFFFFC00 ///< PMC base address.
95 #define RSTC_BASE 0xFFFFFD00 ///< Resect controller register base address.
96 #define RTT_BASE 0xFFFFFD20 ///< Realtime timer base address.
97 #define PIT_BASE 0xFFFFFD30 ///< Periodic interval timer base address.
98 #define WDT_BASE 0xFFFFFD40 ///< Watch Dog register base address.
99 #define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address.
100 #define MC_BASE 0xFFFFFF00 ///< Memory controller base.
102 #define PIO_HAS_MULTIDRIVER 1
103 #define PIO_HAS_PULLUP 1
104 #define PIO_HAS_PERIPHERALSELECT 1
105 #define PIO_HAS_OUTPUTWRITEENABLE 1
107 #define DBGU_HAS_PDC 1
108 #define SPI_HAS_PDC 1
109 #define SSC_HAS_PDC 1
110 #define USART_HAS_PDC 1
112 #include "at91_aic.h"
113 #include "at91_pit.h"
114 #include "at91_pmc.h"
116 #include "at91_wdt.h"
117 #include "at91_rstc.h"
118 #include "at91_pio.h"
120 #include "at91_dbgu.h"
121 //TODO: add other peripherals
124 * Peripheral Identifiers and Interrupts
127 #define FIQ_ID 0 ///< Fast interrupt ID.
128 #define SYSC_ID 1 ///< System controller interrupt.
129 #define PIOA_ID 2 ///< Parallel I/O controller ID.
130 /* ID 3 is reserved */
131 #define ADC_ID 4 ///< Analog to digital converter ID.
132 #define SPI_ID 5 ///< Serial peripheral interface ID.
133 #define US0_ID 6 ///< USART 0 ID.
134 #define US1_ID 7 ///< USART 1 ID.
135 #define SSC_ID 8 ///< Synchronous serial controller ID.
136 #define TWI_ID 9 ///< Two-wire interface ID.
137 #define PWMC_ID 10 ///< PWM controller ID.
138 #define UDP_ID 11 ///< USB device port ID.
139 #define TC0_ID 12 ///< Timer 0 ID.
140 #define TC1_ID 13 ///< Timer 1 ID.
141 #define TC2_ID 14 ///< Timer 2 ID.
143 #define IRQ0_ID 30 ///< External interrupt 0 ID.
144 #define IRQ1_ID 31 ///< External interrupt 1 ID.
161 #define NPCS0 11 // Same as NSS pin.
167 #endif /* AT91SAM7S256_H */