4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific attributes.
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernardo Innocenti <bernie@develer.com>
38 * \author Stefano Fedrigo <aleph@develer.com>
39 * \author Francesco Sacchi <batt@develer.com>
46 #include <cfg/cfg_attr.h> /* CONFIG_FAST_MEM */
47 #include <cfg/compiler.h> /* for uintXX_t */
48 #include <cfg/cfg_arch.h> /* ARCH_EMUL */
52 * \name Macros for determining CPU endianness.
55 #define CPU_BIG_ENDIAN 0x1234
56 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
59 /** Macro to include cpu-specific versions of the headers. */
60 #define CPU_HEADER(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).h)
62 /** Macro to include cpu-specific versions of implementation files. */
63 #define CPU_CSOURCE(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).c)
68 #define NOP nop_instruction()
70 #define CPU_REG_BITS 16
71 #define CPU_REGS_CNT 16
72 #define CPU_STACK_GROWS_UPWARD 0
73 #define CPU_SP_ON_EMPTY_SLOT 0
74 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
79 #define NOP asm volatile ("nop")
81 #define CPU_REGS_CNT 7
82 #define CPU_SAVED_REGS_CNT 7
83 #define CPU_STACK_GROWS_UPWARD 0
84 #define CPU_SP_ON_EMPTY_SLOT 0
85 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
89 #define CPU_REG_BITS 64
92 /* WIN64 is an IL32-P64 weirdo. */
96 #define CPU_REG_BITS 32
101 /* Register counts include SREG too */
102 #define CPU_REG_BITS 32
103 #define CPU_REGS_CNT 16
104 #define CPU_SAVED_REGS_CNT 9
105 #define CPU_STACK_GROWS_UPWARD 0
106 #define CPU_SP_ON_EMPTY_SLOT 0
107 #define CPU_HARVARD 0
109 #ifdef __IAR_SYSTEMS_ICC__
110 #warning Check CPU_BYTE_ORDER
111 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
113 #define NOP __no_operation()
115 #else /* GCC and compatibles */
117 #if defined(__ARMEB__)
118 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
119 #elif defined(__ARMEL__)
120 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
122 #error Unable to detect ARM endianness!
125 #define NOP asm volatile ("mov r0,r0" ::)
128 * Initialization value for registers in stack frame.
129 * The register index is not directly corrispondent to CPU
130 * register numbers, but is related to how are pushed to
131 * stack (\see asm_switch_context).
132 * Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register,
133 * the initial value is set to:
134 * - All flags (N, Z, C, V) set to 0.
135 * - IRQ and FIQ enabled.
137 * - CPU in Supervisor Mode (SVC).
139 #define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
143 * Function attribute for use with performance critical code.
145 * On the AT91 family, code residing in flash has wait states.
146 * Moving functions to the data section is a quick & dirty way
147 * to get them transparently copied to SRAM for zero-wait-state
150 #define FAST_FUNC __attribute__((section(".data")))
153 * Data attribute to move constant data to fast memory storage.
157 #define FAST_RODATA __attribute__((section(".data")))
159 #else // !CONFIG_FAST_MEM
160 #define FAST_RODATA /**/
161 #define FAST_FUNC /**/
165 * Function attribute to declare an interrupt service routine.
167 #define ISR_FUNC __attribute__((interrupt))
169 #endif /* !__IAR_SYSTEMS_ICC_ */
172 #define NOP asm volatile ("nop" ::)
174 /* Register counts include SREG too */
175 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
176 #define CPU_REGS_CNT FIXME
177 #define CPU_SAVED_REGS_CNT FIXME
178 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
179 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
180 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
181 #define CPU_HARVARD 0
187 #define CPU_REG_BITS 16
188 #define CPU_REGS_CNT FIXME
189 #define CPU_SAVED_REGS_CNT 8
190 #define CPU_STACK_GROWS_UPWARD 1
191 #define CPU_SP_ON_EMPTY_SLOT 0
192 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
193 #define CPU_HARVARD 1
195 /* Memory is word-addessed in the DSP56K */
196 #define CPU_BITS_PER_CHAR 16
197 #define SIZEOF_SHORT 1
199 #define SIZEOF_LONG 2
204 #define NOP asm volatile ("nop" ::)
206 /* Register counts include SREG too */
207 #define CPU_REG_BITS 8
208 #define CPU_REGS_CNT 33
209 #define CPU_SAVED_REGS_CNT 19
210 #define CPU_STACK_GROWS_UPWARD 0
211 #define CPU_SP_ON_EMPTY_SLOT 1
212 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
213 #define CPU_HARVARD 1
216 * Initialization value for registers in stack frame.
217 * The register index is not directly corrispondent to CPU
218 * register numbers. Index 0 is the SREG register: the initial
219 * value is all 0 but the interrupt bit (bit 7).
221 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
224 #error No CPU_... defined.
227 /// Default for macro not defined in the right arch section
228 #ifndef CPU_REG_INIT_VALUE
229 #define CPU_REG_INIT_VALUE(reg) 0
232 #ifndef CPU_STACK_GROWS_UPWARD
233 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
236 #ifndef CPU_SP_ON_EMPTY_SLOT
237 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
242 * Function attribute for use with performance critical code.
244 #define FAST_FUNC /* */
249 * Data attribute to move constant data to fast memory storage.
251 #define FAST_RODATA /* */
255 * Support stack handling peculiarities of a few CPUs.
257 * Most processors let their stack grow downward and
258 * keep SP pointing at the last pushed value.
260 #if !CPU_STACK_GROWS_UPWARD
261 #if !CPU_SP_ON_EMPTY_SLOT
262 /* Most microprocessors (x86, m68k...) */
263 #define CPU_PUSH_WORD(sp, data) \
264 do { *--(sp) = (data); } while (0)
265 #define CPU_POP_WORD(sp) \
269 #define CPU_PUSH_WORD(sp, data) \
270 do { *(sp)-- = (data); } while (0)
271 #define CPU_POP_WORD(sp) \
275 #else /* CPU_STACK_GROWS_UPWARD */
277 #if !CPU_SP_ON_EMPTY_SLOT
278 /* DSP56K and other weirdos */
279 #define CPU_PUSH_WORD(sp, data) \
280 do { *++(sp) = (cpustack_t)(data); } while (0)
281 #define CPU_POP_WORD(sp) \
284 #error I bet you cannot find a CPU like this
291 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
292 * RTS discards SR while returning (it does not restore it). So we push
293 * 0 to fake the same context.
295 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
297 CPU_PUSH_WORD((sp), (func)); \
298 CPU_PUSH_WORD((sp), 0x100); \
303 * In AVR, the addresses are pushed into the stack as little-endian, while
304 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
305 * no natural endianess).
307 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
309 uint16_t funcaddr = (uint16_t)(func); \
310 CPU_PUSH_WORD((sp), funcaddr); \
311 CPU_PUSH_WORD((sp), funcaddr>>8); \
315 * If the kernel is in idle-spinning, the processor executes:
321 * IRQ_ENABLE is translated in asm as "sei" and IRQ_DISABLE as "cli".
322 * We could define CPU_IDLE to expand to none, so the resulting
328 * But Atmel datasheet states:
329 * "When using the SEI instruction to enable interrupts,
330 * the instruction following SEI will be executed *before*
331 * any pending interrupts", so "cli" is executed before any
332 * pending interrupt with the result that IRQs will *NOT*
334 * To ensure that IRQ will run a NOP is required.
339 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
340 CPU_PUSH_WORD((sp), (cpustack_t)(func))
346 * \brief Invoked by the scheduler to stop the CPU when idle.
348 * This hook can be redefined to put the CPU in low-power mode, or to
349 * profile system load with an external strobe, or to save CPU cycles
350 * in hosted environments such as emulators.
353 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
354 /* This emulator hook should yield the CPU to the host. */
356 void emul_idle(void);
358 #define CPU_IDLE emul_idle()
359 #else /* !ARCH_EMUL */
360 #define CPU_IDLE do { /* nothing */ } while (0)
361 #endif /* !ARCH_EMUL */
362 #endif /* !CPU_IDLE */
364 #endif /* CPU_ATTR_H */