4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific attributes.
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernardo Innocenti <bernie@develer.com>
38 * \author Stefano Fedrigo <aleph@develer.com>
39 * \author Francesco Sacchi <batt@develer.com>
45 #include <cfg/compiler.h> /* for uintXX_t */
46 #include <cfg/arch_config.h> /* ARCH_EMUL */
50 * \name Macros for determining CPU endianness.
53 #define CPU_BIG_ENDIAN 0x1234
54 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
57 /** Macro to include cpu-specific versions of the headers. */
58 #define CPU_HEADER(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).h)
60 /** Macro to include cpu-specific versions of implementation files. */
61 #define CPU_CSOURCE(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).c)
66 #define NOP nop_instruction()
68 #define CPU_REG_BITS 16
69 #define CPU_REGS_CNT 16
70 #define CPU_STACK_GROWS_UPWARD 0
71 #define CPU_SP_ON_EMPTY_SLOT 0
72 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
77 #define NOP asm volatile ("nop")
79 #define CPU_REGS_CNT 7
80 #define CPU_SAVED_REGS_CNT 7
81 #define CPU_STACK_GROWS_UPWARD 0
82 #define CPU_SP_ON_EMPTY_SLOT 0
83 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
87 #define CPU_REG_BITS 64
90 /* WIN64 is an IL32-P64 weirdo. */
94 #define CPU_REG_BITS 32
99 /* Register counts include SREG too */
100 #define CPU_REG_BITS 32
101 #define CPU_REGS_CNT 16
102 #define CPU_SAVED_REGS_CNT 9
103 #define CPU_STACK_GROWS_UPWARD 0
104 #define CPU_SP_ON_EMPTY_SLOT 0
105 #warning Find a way to detect endianess at runtime
106 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
107 #define CPU_HARVARD 0
109 #ifdef __IAR_SYSTEMS_ICC__
110 #define NOP __no_operation()
111 #else /* !__IAR_SYSTEMS_ICC__ */
112 #define NOP asm volatile ("mov r0,r0" ::)
115 * Initialization value for registers in stack frame.
116 * The register index is not directly corrispondent to CPU
117 * register numbers, but is related to how are pushed to
118 * stack (\see asm_switch_context).
119 * Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register,
120 * the initial value is set to:
121 * - All flags (N, Z, C, V) set to 0.
122 * - IRQ and FIQ enabled.
124 * - CPU in Supervisor Mode (SVC).
126 #define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
128 #endif /* !__IAR_SYSTEMS_ICC_ */
131 #define NOP asm volatile ("nop" ::)
133 /* Register counts include SREG too */
134 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
135 #define CPU_REGS_CNT FIXME
136 #define CPU_SAVED_REGS_CNT FIXME
137 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
138 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
139 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
140 #define CPU_HARVARD 0
146 #define CPU_REG_BITS 16
147 #define CPU_REGS_CNT FIXME
148 #define CPU_SAVED_REGS_CNT 8
149 #define CPU_STACK_GROWS_UPWARD 1
150 #define CPU_SP_ON_EMPTY_SLOT 0
151 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
152 #define CPU_HARVARD 1
154 /* Memory is word-addessed in the DSP56K */
155 #define CPU_BITS_PER_CHAR 16
156 #define SIZEOF_SHORT 1
158 #define SIZEOF_LONG 2
163 #define NOP asm volatile ("nop" ::)
165 /* Register counts include SREG too */
166 #define CPU_REG_BITS 8
167 #define CPU_REGS_CNT 33
168 #define CPU_SAVED_REGS_CNT 19
169 #define CPU_STACK_GROWS_UPWARD 0
170 #define CPU_SP_ON_EMPTY_SLOT 1
171 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
172 #define CPU_HARVARD 1
175 * Initialization value for registers in stack frame.
176 * The register index is not directly corrispondent to CPU
177 * register numbers. Index 0 is the SREG register: the initial
178 * value is all 0 but the interrupt bit (bit 7).
180 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
183 #error No CPU_... defined.
186 /// Default for macro not defined in the right arch section
187 #ifndef CPU_REG_INIT_VALUE
188 #define CPU_REG_INIT_VALUE(reg) 0
192 #ifndef CPU_STACK_GROWS_UPWARD
193 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
196 #ifndef CPU_SP_ON_EMPTY_SLOT
197 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
201 * Support stack handling peculiarities of a few CPUs.
203 * Most processors let their stack grow downward and
204 * keep SP pointing at the last pushed value.
206 #if !CPU_STACK_GROWS_UPWARD
207 #if !CPU_SP_ON_EMPTY_SLOT
208 /* Most microprocessors (x86, m68k...) */
209 #define CPU_PUSH_WORD(sp, data) \
210 do { *--(sp) = (data); } while (0)
211 #define CPU_POP_WORD(sp) \
215 #define CPU_PUSH_WORD(sp, data) \
216 do { *(sp)-- = (data); } while (0)
217 #define CPU_POP_WORD(sp) \
221 #else /* CPU_STACK_GROWS_UPWARD */
223 #if !CPU_SP_ON_EMPTY_SLOT
224 /* DSP56K and other weirdos */
225 #define CPU_PUSH_WORD(sp, data) \
226 do { *++(sp) = (cpustack_t)(data); } while (0)
227 #define CPU_POP_WORD(sp) \
230 #error I bet you cannot find a CPU like this
237 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
238 * RTS discards SR while returning (it does not restore it). So we push
239 * 0 to fake the same context.
241 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
243 CPU_PUSH_WORD((sp), (func)); \
244 CPU_PUSH_WORD((sp), 0x100); \
249 * In AVR, the addresses are pushed into the stack as little-endian, while
250 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
251 * no natural endianess).
253 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
255 uint16_t funcaddr = (uint16_t)(func); \
256 CPU_PUSH_WORD((sp), funcaddr); \
257 CPU_PUSH_WORD((sp), funcaddr>>8); \
261 * If the kernel is in idle-spinning, the processor execute:
267 * IRQ_ENABLE is translated in asm as "sei" and IRQ_DISABLE as "cli".
268 * We could define CPU_IDLE to expand to none, so the resulting
274 * But Atmel datasheet states:
275 * "When using the SEI instruction to enable interrupts,
276 * the instruction following SEI will be executed *before*
277 * any pending interrupts", so "cli" is executed before any
278 * pending interrupt with the result that IRQs will *NOT*
280 * To ensure that IRQ will run a NOP is required.
285 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
286 CPU_PUSH_WORD((sp), (cpustack_t)(func))
292 * \brief Invoked by the scheduler to stop the CPU when idle.
294 * This hook can be redefined to put the CPU in low-power mode, or to
295 * profile system load with an external strobe, or to save CPU cycles
296 * in hosted environments such as emulators.
299 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
300 /* This emulator hook should yield the CPU to the host. */
302 void emul_idle(void);
304 #define CPU_IDLE emul_idle()
305 #else /* !ARCH_EMUL */
306 #define CPU_IDLE do { /* nothing */ } while (0)
307 #endif /* !ARCH_EMUL */
308 #endif /* !CPU_IDLE */
310 #endif /* CPU_ATTR_H */