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29 * Copyright 2003, 2004, 2005 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the AVR ATMega TWI (implementation)
37 * \author Stefano Fedrigo <aleph@develer.com>
38 * \author Bernardo Innocenti <bernie@develer.com>
43 #include <cfg/debug.h>
44 #include <cpu/detect.h>
46 #include <cfg/macros.h> // BV()
47 #include <hw_cpu.h> /* CLOCK_FREQ */
48 #include <appconfig.h>
50 #include <compat/twi.h>
53 /* Wait for TWINT flag set: bus is ready */
54 #define WAIT_TWI_READY do {} while (!(TWCR & BV(TWINT)))
56 #define READ_BIT BV(0)
60 * Send START condition on the bus.
62 * \return true on success, false otherwise.
64 static bool twi_start(void)
66 TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
69 if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
72 kprintf("!TW_(REP)START: %x\n", TWSR);
78 * Send START condition and select slave for write.
79 * \c id is the device id comprehensive of address left shifted by 1.
80 * The LSB of \c id is ignored and reset to 0 for write operation.
82 * \return true on success, false otherwise.
84 bool twi_start_w(uint8_t id)
87 * Loop on the select write sequence: when the eeprom is busy
88 * writing previously sent data it will reply to the SLA_W
89 * control byte with a NACK. In this case, we must
90 * keep trying until the eeprom responds with an ACK.
94 TWDR = id & ~READ_BIT;
95 TWCR = BV(TWINT) | BV(TWEN);
98 if (TW_STATUS == TW_MT_SLA_ACK)
100 else if (TW_STATUS != TW_MT_SLA_NACK)
102 kprintf("!TW_MT_SLA_(N)ACK: %x\n", TWSR);
112 * Send START condition and select slave for read.
113 * \c id is the device id comprehensive of address left shifted by 1.
114 * The LSB of \c id is ignored and set to 1 for read operation.
116 * \return true on success, false otherwise.
118 bool twi_start_r(uint8_t id)
122 TWDR = id | READ_BIT;
123 TWCR = BV(TWINT) | BV(TWEN);
126 if (TW_STATUS == TW_MR_SLA_ACK)
129 kprintf("!TW_MR_SLA_ACK: %x\n", TWSR);
137 * Send STOP condition.
141 TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
146 * Put a single byte in master transmitter mode
147 * to the selected slave device through the TWI bus.
149 * \return true on success, false on error.
151 bool twi_put(const uint8_t data)
154 TWCR = BV(TWINT) | BV(TWEN);
156 if (TW_STATUS != TW_MT_DATA_ACK)
158 kprintf("!TW_MT_DATA_ACK: %x\n", TWSR);
166 * Send a sequence of bytes in master transmitter mode
167 * to the selected slave device through the TWI bus.
169 * \return true on success, false on error.
171 bool twi_send(const void *_buf, size_t count)
173 const uint8_t *buf = (const uint8_t *)_buf;
177 if (!twi_put(*buf++))
185 * Receive a sequence of one or more bytes from the
186 * selected slave device in master receive mode through
189 * Received data is placed in \c buf.
191 * \return true on success, false on error
193 bool twi_recv(void *_buf, size_t count)
195 uint8_t *buf = (uint8_t *)_buf;
198 * When reading the last byte the TWEA bit is not
199 * set, and the eeprom should answer with NACK
203 TWCR = BV(TWINT) | BV(TWEN) | (count ? BV(TWEA) : 0);
208 if (TW_STATUS != TW_MR_DATA_ACK)
210 kprintf("!TW_MR_DATA_ACK: %x\n", TWSR);
216 if (TW_STATUS != TW_MR_DATA_NACK)
218 kprintf("!TW_MR_DATA_NACK: %x\n", TWSR);
230 * Initialize TWI module.
236 * This is pretty useless according to AVR's datasheet,
237 * but it helps us driving the TWI data lines on boards
238 * where the bus pull-up resistors are missing. This is
239 * probably due to some unwanted interaction between the
240 * port pin and the TWI lines.
242 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
243 PORTD |= BV(PD0) | BV(PD1);
244 DDRD |= BV(PD0) | BV(PD1);
245 #elif CPU_AVR_ATMEGA8
246 PORTC |= BV(PC4) | BV(PC5);
247 DDRC |= BV(PC4) | BV(PC5);
249 #error Unsupported architecture
254 * F = CLOCK_FREQ / (16 + 2*TWBR * 4^TWPS)
256 #ifndef CONFIG_TWI_FREQ
257 #warning Using default value of 300000L for CONFIG_TWI_FREQ
258 #define CONFIG_TWI_FREQ 300000L /* ~300 kHz */
260 #define TWI_PRESC 1 /* 4 ^ TWPS */
262 TWBR = (CLOCK_FREQ / (2 * CONFIG_TWI_FREQ * TWI_PRESC)) - (8 / TWI_PRESC);