4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific definitions
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernardo Innocenti <bernie@develer.com>
38 * \author Stefano Fedrigo <aleph@develer.com>
39 * \author Francesco Sacchi <batt@develer.com>
45 #include <cfg/compiler.h> /* for uintXX_t */
46 #include <cfg/arch_config.h> /* ARCH_EMUL */
50 * \name Macros for determining CPU endianness.
53 #define CPU_BIG_ENDIAN 0x1234
54 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
57 /** Macro to include cpu-specific versions of the headers. */
58 #define CPU_HEADER(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).h)
60 /** Macro to include cpu-specific versions of implementation files. */
61 #define CPU_CSOURCE(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).c)
66 #define NOP nop_instruction()
67 #define IRQ_DISABLE disable_interrupt()
68 #define IRQ_ENABLE enable_interrupt()
70 typedef uint16_t cpuflags_t; // FIXME
71 typedef unsigned int cpustack_t;
73 #define CPU_REG_BITS 16
74 #define CPU_REGS_CNT 16
75 #define CPU_STACK_GROWS_UPWARD 0
76 #define CPU_SP_ON_EMPTY_SLOT 0
77 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
82 #define NOP asm volatile ("nop")
84 /* Get IRQ_* definitions from the hosting environment. */
87 #define IRQ_DISABLE FIXME
88 #define IRQ_ENABLE FIXME
89 #define IRQ_SAVE_DISABLE(x) FIXME
90 #define IRQ_RESTORE(x) FIXME
91 typedef uint32_t cpuflags_t; // FIXME
92 #endif /* OS_EMBEDDED */
95 #define CPU_REGS_CNT 7
96 #define CPU_SAVED_REGS_CNT 7
97 #define CPU_STACK_GROWS_UPWARD 0
98 #define CPU_SP_ON_EMPTY_SLOT 0
99 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
100 #define CPU_HARVARD 0
103 typedef uint64_t cpustack_t;
104 #define CPU_REG_BITS 64
107 /* WIN64 is an IL32-P64 weirdo. */
108 #define SIZEOF_LONG 4
111 typedef uint32_t cpustack_t;
112 #define CPU_REG_BITS 32
117 typedef uint32_t cpuflags_t;
118 typedef uint32_t cpustack_t;
120 /* Register counts include SREG too */
121 #define CPU_REG_BITS 32
122 #define CPU_REGS_CNT 16
123 #define CPU_SAVED_REGS_CNT FIXME
124 #define CPU_STACK_GROWS_UPWARD 0
125 #define CPU_SP_ON_EMPTY_SLOT 0
126 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
127 #define CPU_HARVARD 0
129 #ifdef __IAR_SYSTEMS_ICC__
133 #if __CPU_MODE__ == 1 /* Thumb */
135 extern cpuflags_t get_CPSR(void);
136 extern void set_CPSR(cpuflags_t flags);
138 #define get_CPSR __get_CPSR
139 #define set_CPSR __set_CPSR
142 #define NOP __no_operation()
143 #define IRQ_DISABLE __disable_interrupt()
144 #define IRQ_ENABLE __enable_interrupt()
146 #define IRQ_SAVE_DISABLE(x) \
149 __disable_interrupt(); \
152 #define IRQ_RESTORE(x) \
157 #define IRQ_GETSTATE() \
158 ((bool)(get_CPSR() & 0xb0))
160 #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
162 #else /* !__IAR_SYSTEMS_ICC__ */
163 #define NOP asm volatile ("mov r0,r0" ::)
165 #define IRQ_DISABLE \
169 "orr r0, r0, #0xc0\n\t" \
179 "bic r0, r0, #0xc0\n\t" \
185 #define IRQ_SAVE_DISABLE(x) \
189 "orr r0, %0, #0xc0\n\t" \
197 #define IRQ_RESTORE(x) \
206 #define IRQ_GETSTATE() \
214 !((sreg & 0xc0) == 0xc0); \
217 #endif /* !__IAR_SYSTEMS_ICC_ */
220 #define NOP asm volatile ("nop" ::)
222 #define IRQ_DISABLE FIXME
223 #define IRQ_ENABLE FIXME
224 #define IRQ_SAVE_DISABLE(x) FIXME
225 #define IRQ_RESTORE(x) FIXME
226 #define IRQ_GETSTATE() FIXME
228 typedef uint32_t cpuflags_t; // FIXME
229 typedef uint32_t cpustack_t; // FIXME
231 /* Register counts include SREG too */
232 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
233 #define CPU_REGS_CNT FIXME
234 #define CPU_SAVED_REGS_CNT FIXME
235 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
236 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
237 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
238 #define CPU_HARVARD 0
243 #define BREAKPOINT asm(debug)
244 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
245 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
247 #define IRQ_SAVE_DISABLE(x) \
248 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
249 #define IRQ_RESTORE(x) \
250 do { (void)x; asm(move x,SR); } while (0)
252 static inline bool irq_running(void)
254 extern void *user_sp;
257 #define IRQ_RUNNING() irq_running()
259 static inline bool irq_getstate(void)
263 return !(x & 0x0200);
265 #define IRQ_GETSTATE() irq_getstate()
267 typedef uint16_t cpuflags_t;
268 typedef unsigned int cpustack_t;
270 #define CPU_REG_BITS 16
271 #define CPU_REGS_CNT FIXME
272 #define CPU_SAVED_REGS_CNT 8
273 #define CPU_STACK_GROWS_UPWARD 1
274 #define CPU_SP_ON_EMPTY_SLOT 0
275 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
276 #define CPU_HARVARD 1
278 /* Memory is word-addessed in the DSP56K */
279 #define CPU_BITS_PER_CHAR 16
280 #define SIZEOF_SHORT 1
282 #define SIZEOF_LONG 2
287 #define NOP asm volatile ("nop" ::)
288 #define IRQ_DISABLE asm volatile ("cli" ::)
289 #define IRQ_ENABLE asm volatile ("sei" ::)
291 #define IRQ_SAVE_DISABLE(x) \
293 __asm__ __volatile__( \
294 "in %0,__SREG__\n\t" \
296 : "=r" (x) : /* no inputs */ : "cc" \
300 #define IRQ_RESTORE(x) \
302 __asm__ __volatile__( \
303 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
307 #define IRQ_GETSTATE() \
310 __asm__ __volatile__( \
311 "in %0,__SREG__\n\t" \
312 : "=r" (sreg) /* no inputs & no clobbers */ \
314 (bool)(sreg & 0x80); \
317 typedef uint8_t cpuflags_t;
318 typedef uint8_t cpustack_t;
320 /* Register counts include SREG too */
321 #define CPU_REG_BITS 8
322 #define CPU_REGS_CNT 33
323 #define CPU_SAVED_REGS_CNT 19
324 #define CPU_STACK_GROWS_UPWARD 0
325 #define CPU_SP_ON_EMPTY_SLOT 1
326 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
327 #define CPU_HARVARD 1
330 * Initialization value for registers in stack frame.
331 * The register index is not directly corrispondent to CPU
332 * register numbers. Index 0 is the SREG register: the initial
333 * value is all 0 but the interrupt bit (bit 7).
335 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
338 #error No CPU_... defined.
342 * Execute \a CODE atomically with respect to interrupts.
344 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
346 #define ATOMIC(CODE) \
348 cpuflags_t __flags; \
349 IRQ_SAVE_DISABLE(__flags); \
351 IRQ_RESTORE(__flags); \
355 /// Default for macro not defined in the right arch section
356 #ifndef CPU_REG_INIT_VALUE
357 #define CPU_REG_INIT_VALUE(reg) 0
361 #ifndef CPU_STACK_GROWS_UPWARD
362 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
365 #ifndef CPU_SP_ON_EMPTY_SLOT
366 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
370 * Support stack handling peculiarities of a few CPUs.
372 * Most processors let their stack grow downward and
373 * keep SP pointing at the last pushed value.
375 #if !CPU_STACK_GROWS_UPWARD
376 #if !CPU_SP_ON_EMPTY_SLOT
377 /* Most microprocessors (x86, m68k...) */
378 #define CPU_PUSH_WORD(sp, data) \
379 do { *--(sp) = (data); } while (0)
380 #define CPU_POP_WORD(sp) \
384 #define CPU_PUSH_WORD(sp, data) \
385 do { *(sp)-- = (data); } while (0)
386 #define CPU_POP_WORD(sp) \
390 #else /* CPU_STACK_GROWS_UPWARD */
392 #if !CPU_SP_ON_EMPTY_SLOT
393 /* DSP56K and other weirdos */
394 #define CPU_PUSH_WORD(sp, data) \
395 do { *++(sp) = (cpustack_t)(data); } while (0)
396 #define CPU_POP_WORD(sp) \
399 #error I bet you cannot find a CPU like this
406 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
407 * RTS discards SR while returning (it does not restore it). So we push
408 * 0 to fake the same context.
410 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
412 CPU_PUSH_WORD((sp), (func)); \
413 CPU_PUSH_WORD((sp), 0x100); \
418 * In AVR, the addresses are pushed into the stack as little-endian, while
419 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
420 * no natural endianess).
422 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
424 uint16_t funcaddr = (uint16_t)(func); \
425 CPU_PUSH_WORD((sp), funcaddr); \
426 CPU_PUSH_WORD((sp), funcaddr>>8); \
430 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
431 CPU_PUSH_WORD((sp), (cpustack_t)(func))
436 * \name Default type sizes.
438 * These defaults are reasonable for most 16/32bit machines.
439 * Some of these macros may be overridden by CPU-specific code above.
441 * ANSI C requires that the following equations be true:
443 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
444 * sizeof(float) <= sizeof(double)
445 * CPU_BITS_PER_CHAR >= 8
446 * CPU_BITS_PER_SHORT >= 8
447 * CPU_BITS_PER_INT >= 16
448 * CPU_BITS_PER_LONG >= 32
453 #define SIZEOF_CHAR 1
457 #define SIZEOF_SHORT 2
461 #if CPU_REG_BITS < 32
466 #endif /* !SIZEOF_INT */
469 #if CPU_REG_BITS > 32
470 #define SIZEOF_LONG 8
472 #define SIZEOF_LONG 4
477 #if CPU_REG_BITS < 32
479 #elif CPU_REG_BITS == 32
481 #else /* CPU_REG_BITS > 32 */
486 #ifndef CPU_BITS_PER_CHAR
487 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
490 #ifndef CPU_BITS_PER_SHORT
491 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
494 #ifndef CPU_BITS_PER_INT
495 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
498 #ifndef CPU_BITS_PER_LONG
499 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
502 #ifndef CPU_BITS_PER_PTR
503 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
507 #define BREAKPOINT /* nop */
512 /* Sanity checks for the above definitions */
513 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
514 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
515 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
516 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
517 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
518 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
519 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
520 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
521 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
522 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
523 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
524 #ifdef __HAS_INT64_T__
525 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
526 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
532 * \brief Invoked by the scheduler to stop the CPU when idle.
534 * This hook can be redefined to put the CPU in low-power mode, or to
535 * profile system load with an external strobe, or to save CPU cycles
536 * in hosted environments such as emulators.
539 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
540 /* This emulator hook should yield the CPU to the host. */
542 void emul_idle(void);
544 #define CPU_IDLE emul_idle()
545 #else /* !ARCH_EMUL */
546 #define CPU_IDLE do { /* nothing */ } while (0)
547 #endif /* !ARCH_EMUL */
548 #endif /* !CPU_IDLE */
550 #endif /* CPU_CPU_H */