4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific definitions
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernardo Innocenti <bernie@develer.com>
38 * \author Stefano Fedrigo <aleph@develer.com>
39 * \author Francesco Sacchi <batt@develer.com>
45 #include <cfg/compiler.h> /* for uintXX_t */
46 #include <cfg/arch_config.h> /* ARCH_EMUL */
50 * \name Macros for determining CPU endianness.
53 #define CPU_BIG_ENDIAN 0x1234
54 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
57 /** Macro to include cpu-specific versions of the headers. */
58 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
60 /** Macro to include cpu-specific versions of implementation files. */
61 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
66 #define NOP nop_instruction()
67 #define IRQ_DISABLE disable_interrupt()
68 #define IRQ_ENABLE enable_interrupt()
70 typedef uint16_t cpuflags_t; // FIXME
71 typedef unsigned int cpustack_t;
73 #define CPU_REG_BITS 16
74 #define CPU_REGS_CNT 16
75 #define CPU_STACK_GROWS_UPWARD 0
76 #define CPU_SP_ON_EMPTY_SLOT 0
77 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
82 #define NOP asm volatile ("nop")
84 /* Get IRQ_* definitions from the hosting environment. */
87 #define IRQ_DISABLE FIXME
88 #define IRQ_ENABLE FIXME
89 #define IRQ_SAVE_DISABLE(x) FIXME
90 #define IRQ_RESTORE(x) FIXME
91 typedef uint32_t cpuflags_t; // FIXME
92 #endif /* OS_EMBEDDED */
95 #define CPU_REGS_CNT 7
96 #define CPU_SAVED_REGS_CNT 7
97 #define CPU_STACK_GROWS_UPWARD 0
98 #define CPU_SP_ON_EMPTY_SLOT 0
99 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
100 #define CPU_HARVARD 0
103 typedef uint64_t cpustack_t;
104 #define CPU_REG_BITS 64
107 /* WIN64 is an IL32-P64 weirdo. */
108 #define SIZEOF_LONG 4
111 typedef uint32_t cpustack_t;
112 #define CPU_REG_BITS 32
117 typedef uint32_t cpuflags_t;
118 typedef uint32_t cpustack_t;
120 /* Register counts include SREG too */
121 #define CPU_REG_BITS 32
122 #define CPU_REGS_CNT 16
123 #define CPU_SAVED_REGS_CNT FIXME
124 #define CPU_STACK_GROWS_UPWARD 0
125 #define CPU_SP_ON_EMPTY_SLOT 0
126 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
127 #define CPU_HARVARD 0
129 #ifdef __IAR_SYSTEMS_ICC__
133 #if __CPU_MODE__ == 1 /* Thumb */
135 extern cpuflags_t get_CPSR(void);
136 extern void set_CPSR(cpuflags_t flags);
138 #define get_CPSR __get_CPSR
139 #define set_CPSR __set_CPSR
142 #define NOP __no_operation()
143 #define IRQ_DISABLE __disable_interrupt()
144 #define IRQ_ENABLE __enable_interrupt()
146 #define IRQ_SAVE_DISABLE(x) \
149 __disable_interrupt(); \
152 #define IRQ_RESTORE(x) \
157 #define IRQ_GETSTATE() \
158 ((bool)(get_CPSR() & 0xb0))
160 #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
162 #else /* !__IAR_SYSTEMS_ICC__ */
164 #warning "IRQ_ macros need testing!"
165 #warning "Test now or die :-)"
167 #define NOP asm volatile ("mov r0,r0" ::)
169 #define IRQ_DISABLE \
173 "orr r0, r0, #0xc0\n\t" \
183 "bic r0, r0, #0xc0\n\t" \
189 #define IRQ_SAVE_DISABLE(x) \
193 "orr r0, %0, #0xc0\n\t" \
201 #define IRQ_RESTORE(x) \
210 #define IRQ_GETSTATE() \
218 !((sreg & 0xc0) == 0xc0); \
221 #endif /* !__IAR_SYSTEMS_ICC_ */
224 #define NOP asm volatile ("nop" ::)
226 #define IRQ_DISABLE FIXME
227 #define IRQ_ENABLE FIXME
228 #define IRQ_SAVE_DISABLE(x) FIXME
229 #define IRQ_RESTORE(x) FIXME
230 #define IRQ_GETSTATE() FIXME
232 typedef uint32_t cpuflags_t; // FIXME
233 typedef uint32_t cpustack_t; // FIXME
235 /* Register counts include SREG too */
236 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
237 #define CPU_REGS_CNT FIXME
238 #define CPU_SAVED_REGS_CNT FIXME
239 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
240 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
241 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
242 #define CPU_HARVARD 0
247 #define BREAKPOINT asm(debug)
248 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
249 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
251 #define IRQ_SAVE_DISABLE(x) \
252 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
253 #define IRQ_RESTORE(x) \
254 do { (void)x; asm(move x,SR); } while (0)
256 static inline bool irq_running(void)
258 extern void *user_sp;
261 #define IRQ_RUNNING() irq_running()
263 static inline bool irq_getstate(void)
267 return !(x & 0x0200);
269 #define IRQ_GETSTATE() irq_getstate()
271 typedef uint16_t cpuflags_t;
272 typedef unsigned int cpustack_t;
274 #define CPU_REG_BITS 16
275 #define CPU_REGS_CNT FIXME
276 #define CPU_SAVED_REGS_CNT 8
277 #define CPU_STACK_GROWS_UPWARD 1
278 #define CPU_SP_ON_EMPTY_SLOT 0
279 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
280 #define CPU_HARVARD 1
282 /* Memory is word-addessed in the DSP56K */
283 #define CPU_BITS_PER_CHAR 16
284 #define SIZEOF_SHORT 1
286 #define SIZEOF_LONG 2
291 #define NOP asm volatile ("nop" ::)
292 #define IRQ_DISABLE asm volatile ("cli" ::)
293 #define IRQ_ENABLE asm volatile ("sei" ::)
295 #define IRQ_SAVE_DISABLE(x) \
297 __asm__ __volatile__( \
298 "in %0,__SREG__\n\t" \
300 : "=r" (x) : /* no inputs */ : "cc" \
304 #define IRQ_RESTORE(x) \
306 __asm__ __volatile__( \
307 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
311 #define IRQ_GETSTATE() \
314 __asm__ __volatile__( \
315 "in %0,__SREG__\n\t" \
316 : "=r" (sreg) /* no inputs & no clobbers */ \
318 (bool)(sreg & 0x80); \
321 typedef uint8_t cpuflags_t;
322 typedef uint8_t cpustack_t;
324 /* Register counts include SREG too */
325 #define CPU_REG_BITS 8
326 #define CPU_REGS_CNT 33
327 #define CPU_SAVED_REGS_CNT 19
328 #define CPU_STACK_GROWS_UPWARD 0
329 #define CPU_SP_ON_EMPTY_SLOT 1
330 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
331 #define CPU_HARVARD 1
334 * Initialization value for registers in stack frame.
335 * The register index is not directly corrispondent to CPU
336 * register numbers. Index 0 is the SREG register: the initial
337 * value is all 0 but the interrupt bit (bit 7).
339 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
342 #error No CPU_... defined.
346 * Execute \a CODE atomically with respect to interrupts.
348 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
350 #define ATOMIC(CODE) \
352 cpuflags_t __flags; \
353 IRQ_SAVE_DISABLE(__flags); \
355 IRQ_RESTORE(__flags); \
359 /// Default for macro not defined in the right arch section
360 #ifndef CPU_REG_INIT_VALUE
361 #define CPU_REG_INIT_VALUE(reg) 0
365 #ifndef CPU_STACK_GROWS_UPWARD
366 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
369 #ifndef CPU_SP_ON_EMPTY_SLOT
370 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
374 * Support stack handling peculiarities of a few CPUs.
376 * Most processors let their stack grow downward and
377 * keep SP pointing at the last pushed value.
379 #if !CPU_STACK_GROWS_UPWARD
380 #if !CPU_SP_ON_EMPTY_SLOT
381 /* Most microprocessors (x86, m68k...) */
382 #define CPU_PUSH_WORD(sp, data) \
383 do { *--(sp) = (data); } while (0)
384 #define CPU_POP_WORD(sp) \
388 #define CPU_PUSH_WORD(sp, data) \
389 do { *(sp)-- = (data); } while (0)
390 #define CPU_POP_WORD(sp) \
394 #else /* CPU_STACK_GROWS_UPWARD */
396 #if !CPU_SP_ON_EMPTY_SLOT
397 /* DSP56K and other weirdos */
398 #define CPU_PUSH_WORD(sp, data) \
399 do { *++(sp) = (cpustack_t)(data); } while (0)
400 #define CPU_POP_WORD(sp) \
403 #error I bet you cannot find a CPU like this
410 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
411 * RTS discards SR while returning (it does not restore it). So we push
412 * 0 to fake the same context.
414 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
416 CPU_PUSH_WORD((sp), (func)); \
417 CPU_PUSH_WORD((sp), 0x100); \
422 * In AVR, the addresses are pushed into the stack as little-endian, while
423 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
424 * no natural endianess).
426 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
428 uint16_t funcaddr = (uint16_t)(func); \
429 CPU_PUSH_WORD((sp), funcaddr); \
430 CPU_PUSH_WORD((sp), funcaddr>>8); \
434 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
435 CPU_PUSH_WORD((sp), (cpustack_t)(func))
440 * \name Default type sizes.
442 * These defaults are reasonable for most 16/32bit machines.
443 * Some of these macros may be overridden by CPU-specific code above.
445 * ANSI C requires that the following equations be true:
447 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
448 * sizeof(float) <= sizeof(double)
449 * CPU_BITS_PER_CHAR >= 8
450 * CPU_BITS_PER_SHORT >= 8
451 * CPU_BITS_PER_INT >= 16
452 * CPU_BITS_PER_LONG >= 32
457 #define SIZEOF_CHAR 1
461 #define SIZEOF_SHORT 2
465 #if CPU_REG_BITS < 32
470 #endif /* !SIZEOF_INT */
473 #if CPU_REG_BITS > 32
474 #define SIZEOF_LONG 8
476 #define SIZEOF_LONG 4
481 #if CPU_REG_BITS < 32
483 #elif CPU_REG_BITS == 32
485 #else /* CPU_REG_BITS > 32 */
490 #ifndef CPU_BITS_PER_CHAR
491 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
494 #ifndef CPU_BITS_PER_SHORT
495 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
498 #ifndef CPU_BITS_PER_INT
499 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
502 #ifndef CPU_BITS_PER_LONG
503 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
506 #ifndef CPU_BITS_PER_PTR
507 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
511 #define BREAKPOINT /* nop */
516 /* Sanity checks for the above definitions */
517 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
518 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
519 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
520 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
521 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
522 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
523 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
524 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
525 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
526 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
527 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
528 #ifdef __HAS_INT64_T__
529 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
530 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
536 * \brief Invoked by the scheduler to stop the CPU when idle.
538 * This hook can be redefined to put the CPU in low-power mode, or to
539 * profile system load with an external strobe, or to save CPU cycles
540 * in hosted environments such as emulators.
543 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
544 /* This emulator hook should yield the CPU to the host. */
546 void emul_idle(void);
548 #define CPU_IDLE emul_idle()
549 #else /* !ARCH_EMUL */
550 #define CPU_IDLE do { /* nothing */ } while (0)
551 #endif /* !ARCH_EMUL */
552 #endif /* !CPU_IDLE */
554 #endif /* CPU_CPU_H */