cpu/irq.h

   1 /**
   2  * \file
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   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
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  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
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  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  *
  20  * As a special exception, you may use this file as part of a free software
  21  * library without restriction.  Specifically, if other files instantiate
  22  * templates or use macros or inline functions from this file, or you compile
  23  * this file and link it with other files to produce an executable, this
  24  * file does not by itself cause the resulting executable to be covered by
  25  * the GNU General Public License.  This exception does not however
  26  * invalidate any other reasons why the executable file might be covered by
  27  * the GNU General Public License.
  28  *
  29  * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
  30  * Copyright 2004 Giovanni Bajo
  31  *
  32  * -->
  33  *
  34  * \brief CPU-specific IRQ definitions.
  35  *
  36  * \author Giovanni Bajo <rasky@develer.com>
  37  * \author Bernardo Innocenti <bernie@develer.com>
  38  * \author Stefano Fedrigo <aleph@develer.com>
  39  * \author Francesco Sacchi <batt@develer.com>
  40  */
  41 #ifndef CPU_IRQ_H
  42 #define CPU_IRQ_H
  43
  44 #include "detect.h"
  45 #include "types.h"
  46
  47 #include <cfg/compiler.h> /* for uintXX_t */
  48
  49 #if CPU_I196
  50         #define IRQ_DISABLE             disable_interrupt()
  51         #define IRQ_ENABLE              enable_interrupt()
  52 #elif CPU_X86
  53
  54         /* Get IRQ_* definitions from the hosting environment. */
  55         #include <cfg/os.h>
  56         #if OS_EMBEDDED
  57                 #define IRQ_DISABLE             FIXME
  58                 #define IRQ_ENABLE              FIXME
  59                 #define IRQ_SAVE_DISABLE(x)     FIXME
  60                 #define IRQ_RESTORE(x)          FIXME
  61         #endif /* OS_EMBEDDED */
  62
  63 #elif CPU_ARM
  64
  65
  66         #ifdef __IAR_SYSTEMS_ICC__
  67
  68                 #include <inarm.h>
  69
  70                 #if __CPU_MODE__ == 1 /* Thumb */
  71                         /* Use stubs */
  72                         extern cpuflags_t get_CPSR(void);
  73                         extern void set_CPSR(cpuflags_t flags);
  74                 #else
  75                         #define get_CPSR __get_CPSR
  76                         #define set_CPSR __set_CPSR
  77                 #endif
  78
  79                 #define IRQ_DISABLE __disable_interrupt()
  80                 #define IRQ_ENABLE  __enable_interrupt()
  81
  82                 #define IRQ_SAVE_DISABLE(x) \
  83                 do { \
  84                         (x) = get_CPSR(); \
  85                         __disable_interrupt(); \
  86                 } while (0)
  87
  88                 #define IRQ_RESTORE(x) \
  89                 do { \
  90                         set_CPSR(x); \
  91                 } while (0)
  92
  93                 #define IRQ_ENABLED() \
  94                         ((bool)(get_CPSR() & 0xb0))
  95
  96                 #define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
  97
  98         #else /* !__IAR_SYSTEMS_ICC__ */
  99
 100                 #define IRQ_DISABLE \
 101                 do { \
 102                         asm volatile ( \
 103                                 "mrs r0, cpsr\n\t" \
 104                                 "orr r0, r0, #0xc0\n\t" \
 105                                 "msr cpsr_c, r0" \
 106                                 ::: "r0" \
 107                         ); \
 108                 } while (0)
 109
 110                 #define IRQ_ENABLE \
 111                 do { \
 112                         asm volatile ( \
 113                                 "mrs r0, cpsr\n\t" \
 114                                 "bic r0, r0, #0xc0\n\t" \
 115                                 "msr cpsr_c, r0" \
 116                                 ::: "r0" \
 117                         ); \
 118                 } while (0)
 119
 120                 #define IRQ_SAVE_DISABLE(x) \
 121                 do { \
 122                         asm volatile ( \
 123                                 "mrs %0, cpsr\n\t" \
 124                                 "orr r0, %0, #0xc0\n\t" \
 125                                 "msr cpsr_c, r0" \
 126                                 : "=r" (x) \
 127                                 : /* no inputs */ \
 128                                 : "r0" \
 129                         ); \
 130                 } while (0)
 131
 132                 #define IRQ_RESTORE(x) \
 133                 do { \
 134                         asm volatile ( \
 135                                 "msr cpsr_c, %0" \
 136                                 : /* no outputs */ \
 137                                 : "r" (x) \
 138                         ); \
 139                 } while (0)
 140
 141                 #define CPU_READ_FLAGS() \
 142                 ({ \
 143                         cpuflags_t sreg; \
 144                         asm volatile ( \
 145                                 "mrs %0, cpsr\n\t" \
 146                                 : "=r" (sreg) \
 147                                 : /* no inputs */ \
 148                         ); \
 149                         sreg; \
 150                 })
 151
 152                 #define IRQ_ENABLED() ((CPU_READ_FLAGS() & 0xc0) != 0xc0)
 153
 154                 /**
 155                  * Interrupt entry point.
 156                  * Needed because AT91 uses an Interrupt Controller with auto-vectoring.
 157                  */
 158                 #define IRQ_ENTRY() \
 159                         asm volatile("sub   lr, lr,#4"          "\n\t"  /* Adjust LR */ \
 160                                 "stmfd sp!,{r0-r12,lr}"    "\n\t"  /* Save registers on IRQ stack. */ \
 161                                 "mrs   r1, spsr"           "\n\t"  /* Save SPSR */ \
 162                                 "stmfd sp!,{r1}"           "\n\t")     /* */
 163
 164                 /**
 165                  * Interrupt exit.
 166                  * Needed because AT91 uses an Interrupt Controller with auto-vectoring.
 167                  */
 168                 #define IRQ_EXIT() \
 169                         asm volatile("ldmfd sp!, {r1}"          "\n\t"  /* Restore SPSR */ \
 170                                 "msr   spsr_c, r1"         "\n\t"  /* */ \
 171                                 "ldr   r0, =0xFFFFF000"    "\n\t"  /* End of interrupt. */ \
 172                                 "str   r0, [r0, #0x130]"   "\n\t"  /* */ \
 173                                 "ldmfd sp!, {r0-r12, pc}^" "\n\t")     /* Restore registers and return. */
 174
 175
 176         #endif /* !__IAR_SYSTEMS_ICC_ */
 177
 178 #elif CPU_PPC
 179         #define IRQ_DISABLE         FIXME
 180         #define IRQ_ENABLE          FIXME
 181         #define IRQ_SAVE_DISABLE(x) FIXME
 182         #define IRQ_RESTORE(x)      FIXME
 183         #define IRQ_ENABLED()      FIXME
 184
 185 #elif CPU_DSP56K
 186
 187         #define BREAKPOINT              asm(debug)
 188         #define IRQ_DISABLE             do { asm(bfset #0x0200,SR); asm(nop); } while (0)
 189         #define IRQ_ENABLE              do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
 190
 191         #define IRQ_SAVE_DISABLE(x)  \
 192                 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
 193         #define IRQ_RESTORE(x)  \
 194                 do { (void)x; asm(move x,SR); } while (0)
 195
 196         static inline bool irq_running(void)
 197         {
 198                 extern void *user_sp;
 199                 return !!user_sp;
 200         }
 201         #define IRQ_RUNNING() irq_running()
 202
 203         static inline bool irq_enabled(void)
 204         {
 205                 uint16_t x;
 206                 asm(move SR,x);
 207                 return !(x & 0x0200);
 208         }
 209         #define IRQ_ENABLED() irq_enabled()
 210
 211 #elif CPU_AVR
 212
 213         #define IRQ_DISABLE   asm volatile ("cli" ::)
 214         #define IRQ_ENABLE    asm volatile ("sei" ::)
 215
 216         #define IRQ_SAVE_DISABLE(x) \
 217         do { \
 218                 __asm__ __volatile__( \
 219                         "in %0,__SREG__\n\t" \
 220                         "cli" \
 221                         : "=r" (x) : /* no inputs */ : "cc" \
 222                 ); \
 223         } while (0)
 224
 225         #define IRQ_RESTORE(x) \
 226         do { \
 227                 __asm__ __volatile__( \
 228                         "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
 229                 ); \
 230         } while (0)
 231
 232         #define IRQ_ENABLED() \
 233         ({ \
 234                 uint8_t sreg; \
 235                 __asm__ __volatile__( \
 236                         "in %0,__SREG__\n\t" \
 237                         : "=r" (sreg)  /* no inputs & no clobbers */ \
 238                 ); \
 239                 (bool)(sreg & 0x80); \
 240         })
 241 #else
 242         #error No CPU_... defined.
 243 #endif
 244
 245 #ifndef IRQ_ENTRY
 246         #define IRQ_ENTRY() /* NOP */
 247 #endif
 248
 249 #ifndef IRQ_EXIT
 250         #define IRQ_EXIT() /* NOP */
 251 #endif
 252
 253
 254 /**
 255  * Execute \a CODE atomically with respect to interrupts.
 256  *
 257  * \see IRQ_SAVE_DISABLE IRQ_RESTORE
 258  */
 259 #define ATOMIC(CODE) \
 260         do { \
 261                 cpuflags_t __flags; \
 262                 IRQ_SAVE_DISABLE(__flags); \
 263                 CODE; \
 264                 IRQ_RESTORE(__flags); \
 265         } while (0)
 266
 267
 268 #ifndef BREAKPOINT
 269 #define BREAKPOINT /* nop */
 270 #endif
 271
 272
 273 #endif /* CPU_IRQ_H */