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29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific IRQ definitions.
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernardo Innocenti <bernie@develer.com>
38 * \author Stefano Fedrigo <aleph@develer.com>
39 * \author Francesco Sacchi <batt@develer.com>
47 #include <cfg/compiler.h> /* for uintXX_t */
50 #define IRQ_DISABLE disable_interrupt()
51 #define IRQ_ENABLE enable_interrupt()
54 /* Get IRQ_* definitions from the hosting environment. */
57 #define IRQ_DISABLE FIXME
58 #define IRQ_ENABLE FIXME
59 #define IRQ_SAVE_DISABLE(x) FIXME
60 #define IRQ_RESTORE(x) FIXME
61 #endif /* OS_EMBEDDED */
66 #ifdef __IAR_SYSTEMS_ICC__
70 #if __CPU_MODE__ == 1 /* Thumb */
72 extern cpuflags_t get_CPSR(void);
73 extern void set_CPSR(cpuflags_t flags);
75 #define get_CPSR __get_CPSR
76 #define set_CPSR __set_CPSR
79 #define IRQ_DISABLE __disable_interrupt()
80 #define IRQ_ENABLE __enable_interrupt()
82 #define IRQ_SAVE_DISABLE(x) \
85 __disable_interrupt(); \
88 #define IRQ_RESTORE(x) \
93 #define IRQ_ENABLED() \
94 ((bool)(get_CPSR() & 0xb0))
96 #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
98 #else /* !__IAR_SYSTEMS_ICC__ */
100 #define IRQ_DISABLE \
104 "orr r0, r0, #0xc0\n\t" \
114 "bic r0, r0, #0xc0\n\t" \
120 #define IRQ_SAVE_DISABLE(x) \
124 "orr r0, %0, #0xc0\n\t" \
132 #define IRQ_RESTORE(x) \
141 #define CPU_READ_FLAGS() \
152 #define IRQ_ENABLED() ((CPU_READ_FLAGS() & 0xc0) != 0xc0)
155 * Interrupt entry point.
156 * Needed because AT91 uses an Interrupt Controller with auto-vectoring.
158 #define IRQ_ENTRY() \
159 asm volatile("sub lr, lr,#4" "\n\t" /* Adjust LR */ \
160 "stmfd sp!,{r0-r12,lr}" "\n\t" /* Save registers on IRQ stack. */ \
161 "mrs r1, spsr" "\n\t" /* Save SPSR */ \
162 "stmfd sp!,{r1}" "\n\t") /* */
166 * Needed because AT91 uses an Interrupt Controller with auto-vectoring.
169 asm volatile("ldmfd sp!, {r1}" "\n\t" /* Restore SPSR */ \
170 "msr spsr_c, r1" "\n\t" /* */ \
171 "ldr r0, =0xFFFFF000" "\n\t" /* End of interrupt. */ \
172 "str r0, [r0, #0x130]" "\n\t" /* */ \
173 "ldmfd sp!, {r0-r12, pc}^" "\n\t") /* Restore registers and return. */
176 #endif /* !__IAR_SYSTEMS_ICC_ */
179 #define IRQ_DISABLE FIXME
180 #define IRQ_ENABLE FIXME
181 #define IRQ_SAVE_DISABLE(x) FIXME
182 #define IRQ_RESTORE(x) FIXME
183 #define IRQ_ENABLED() FIXME
187 #define BREAKPOINT asm(debug)
188 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
189 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
191 #define IRQ_SAVE_DISABLE(x) \
192 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
193 #define IRQ_RESTORE(x) \
194 do { (void)x; asm(move x,SR); } while (0)
196 static inline bool irq_running(void)
198 extern void *user_sp;
201 #define IRQ_RUNNING() irq_running()
203 static inline bool irq_enabled(void)
207 return !(x & 0x0200);
209 #define IRQ_ENABLED() irq_enabled()
213 #define IRQ_DISABLE asm volatile ("cli" ::)
214 #define IRQ_ENABLE asm volatile ("sei" ::)
216 #define IRQ_SAVE_DISABLE(x) \
218 __asm__ __volatile__( \
219 "in %0,__SREG__\n\t" \
221 : "=r" (x) : /* no inputs */ : "cc" \
225 #define IRQ_RESTORE(x) \
227 __asm__ __volatile__( \
228 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
232 #define IRQ_ENABLED() \
235 __asm__ __volatile__( \
236 "in %0,__SREG__\n\t" \
237 : "=r" (sreg) /* no inputs & no clobbers */ \
239 (bool)(sreg & 0x80); \
242 #error No CPU_... defined.
246 #define IRQ_ENTRY() /* NOP */
250 #define IRQ_EXIT() /* NOP */
255 * Execute \a CODE atomically with respect to interrupts.
257 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
259 #define ATOMIC(CODE) \
261 cpuflags_t __flags; \
262 IRQ_SAVE_DISABLE(__flags); \
264 IRQ_RESTORE(__flags); \
269 #define BREAKPOINT /* nop */
273 #endif /* CPU_IRQ_H */