4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.28 2004/12/31 17:39:41 bernie
21 *#* Fix documentation.
23 *#* Revision 1.27 2004/12/31 17:02:47 bernie
24 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
26 *#* Revision 1.26 2004/12/13 12:08:12 bernie
27 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
29 *#* Revision 1.25 2004/12/08 08:31:02 bernie
30 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
32 *#* Revision 1.24 2004/12/08 08:04:13 bernie
35 *#* Revision 1.23 2004/11/16 22:41:58 bernie
36 *#* Support 64bit CPUs.
38 *#* Revision 1.22 2004/11/16 21:57:59 bernie
39 *#* CPU_IDLE: Rename from SCHEDULER_IDLE.
41 *#* Revision 1.21 2004/11/16 21:34:25 bernie
42 *#* Commonize obsolete names for IRQ macros; Doxygen fixes.
44 *#* Revision 1.20 2004/11/16 20:33:32 bernie
45 *#* CPU_HARVARD: New macro.
47 *#* Revision 1.19 2004/10/03 20:43:54 bernie
48 *#* Fix Doxygen markup.
50 *#* Revision 1.18 2004/10/03 18:36:31 bernie
51 *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
53 *#* Revision 1.17 2004/09/06 21:48:27 bernie
54 *#* ATOMIC(): New macro.
56 *#* Revision 1.16 2004/08/29 21:58:33 bernie
57 *#* Rename BITS_PER_XYZ macros; Add sanity checks.
59 *#* Revision 1.15 2004/08/25 14:12:08 rasky
60 *#* Aggiornato il comment block dei log RCS
62 *#* Revision 1.14 2004/08/24 13:29:28 bernie
63 *#* Trim CVS log; Rename header guards.
65 *#* Revision 1.12 2004/08/14 19:37:57 rasky
66 *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
68 *#* Revision 1.11 2004/08/05 17:39:56 bernie
69 *#* Fix a Doxygen tag.
71 *#* Revision 1.10 2004/08/02 20:20:29 aleph
72 *#* Merge from project_ks
74 *#* Revision 1.9 2004/07/30 14:24:16 rasky
75 *#* Task switching con salvataggio perfetto stato di interrupt (SR)
76 *#* Kernel monitor per dump informazioni su stack dei processi
81 #include "compiler.h" /* for uintXX_t */
85 * \name Macros for determining CPU endianness.
88 #define CPU_BIG_ENDIAN 0x1234
89 #define CPU_LITTLE_ENDIAN 0x3412
92 /*! Macro to include cpu-specific versions of the headers. */
93 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
98 #define NOP nop_instruction()
99 #define IRQ_DISABLE disable_interrupt()
100 #define IRQ_ENABLE enable_interrupt()
102 typedef uint16_t cpuflags_t; // FIXME
103 typedef unsigned int cpustack_t;
105 #define CPU_REG_BITS 16
106 #define CPU_REGS_CNT 16
107 #define CPU_STACK_GROWS_UPWARD 0
108 #define CPU_SP_ON_EMPTY_SLOT 0
109 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
110 #define CPU_HARVARD 0
114 #define NOP asm volatile ("nop")
115 #define IRQ_DISABLE /* nothing */
116 #define IRQ_ENABLE /* nothing */
117 #define IRQ_SAVE_DISABLE(x) /* nothing */
118 #define IRQ_RESTORE(x) /* nothing */
120 typedef uint32_t cpuflags_t; // FIXME
121 typedef uint32_t cpustack_t;
123 #define CPU_REG_BITS 32
124 #define CPU_REGS_CNT 7
125 #define CPU_STACK_GROWS_UPWARD 0
126 #define CPU_SP_ON_EMPTY_SLOT 0
127 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
128 #define CPU_HARVARD 0
133 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
134 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
136 #define IRQ_SAVE_DISABLE(x) \
137 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
138 #define IRQ_RESTORE(x) \
139 do { (void)x; asm(move x,SR); } while (0)
142 typedef uint16_t cpuflags_t;
143 typedef unsigned int cpustack_t;
145 #define CPU_REG_BITS 16
146 #define CPU_REGS_CNT FIXME
147 #define CPU_SAVED_REGS_CNT 8
148 #define CPU_STACK_GROWS_UPWARD 1
149 #define CPU_SP_ON_EMPTY_SLOT 0
150 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
151 #define CPU_HARVARD 1
153 /* Memory is word-addessed in the DSP56K */
154 #define CPU_BITS_PER_CHAR 16
155 #define SIZEOF_SHORT 1
157 #define SIZEOF_LONG 2
162 #define NOP asm volatile ("nop" ::)
163 #define IRQ_DISABLE asm volatile ("cli" ::)
164 #define IRQ_ENABLE asm volatile ("sei" ::)
166 #define IRQ_SAVE_DISABLE(x) \
168 __asm__ __volatile__( \
169 "in %0,__SREG__\n\t" \
171 : "=r" (x) : /* no inputs */ : "cc" \
175 #define IRQ_RESTORE(x) \
177 __asm__ __volatile__( \
178 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
182 #define IRQ_GETSTATE() \
185 __asm__ __volatile__( \
186 "in %0,__SREG__\n\t" \
187 : "=r" (sreg) /* no inputs & no clobbers */ \
189 (bool)(sreg & 0x80); \
192 typedef uint8_t cpuflags_t;
193 typedef uint8_t cpustack_t;
195 /* Register counts include SREG too */
196 #define CPU_REG_BITS 8
197 #define CPU_REGS_CNT 33
198 #define CPU_SAVED_REGS_CNT 19
199 #define CPU_STACK_GROWS_UPWARD 0
200 #define CPU_SP_ON_EMPTY_SLOT 1
201 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
202 #define CPU_HARVARD 1
205 * Initialization value for registers in stack frame.
206 * The register index is not directly corrispondent to CPU
207 * register numbers. Index 0 is the SREG register: the initial
208 * value is all 0 but the interrupt bit (bit 7).
210 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
215 * Execute \a CODE atomically with respect to interrupts.
217 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
219 #define ATOMIC(CODE) \
221 cpuflags_t __flags; \
222 IRQ_SAVE_DISABLE(__flags); \
224 IRQ_RESTORE(__flags); \
228 //! Default for macro not defined in the right arch section
229 #ifndef CPU_REG_INIT_VALUE
230 #define CPU_REG_INIT_VALUE(reg) 0
234 #ifndef CPU_STACK_GROWS_UPWARD
235 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
238 #ifndef CPU_SP_ON_EMPTY_SLOT
239 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
243 * Support stack handling peculiarities of a few CPUs.
245 * Most processors let their stack grow downward and
246 * keep SP pointing at the last pushed value.
248 #if !CPU_STACK_GROWS_UPWARD
249 #if !CPU_SP_ON_EMPTY_SLOT
250 /* Most microprocessors (x86, m68k...) */
251 #define CPU_PUSH_WORD(sp, data) \
252 do { *--(sp) = (data); } while (0)
253 #define CPU_POP_WORD(sp) \
257 #define CPU_PUSH_WORD(sp, data) \
258 do { *(sp)-- = (data); } while (0)
259 #define CPU_POP_WORD(sp) \
263 #else /* CPU_STACK_GROWS_UPWARD */
265 #if !CPU_SP_ON_EMPTY_SLOT
266 /* DSP56K and other weirdos */
267 #define CPU_PUSH_WORD(sp, data) \
268 do { *++(sp) = (cpustack_t)(data); } while (0)
269 #define CPU_POP_WORD(sp) \
272 #error I bet you cannot find a CPU like this
279 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
280 * RTS discards SR while returning (it does not restore it). So we push
281 * 0 to fake the same context.
283 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
285 CPU_PUSH_WORD((sp), (func)); \
286 CPU_PUSH_WORD((sp), 0x100); \
291 * In AVR, the addresses are pushed into the stack as little-endian, while
292 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
293 * no natural endianess).
295 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
297 uint16_t funcaddr = (uint16_t)(func); \
298 CPU_PUSH_WORD((sp), funcaddr); \
299 CPU_PUSH_WORD((sp), funcaddr>>8); \
303 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
304 CPU_PUSH_WORD((sp), (func))
309 * \name Default type sizes.
311 * These defaults are reasonable for most 16/32bit machines.
312 * Some of these macros may be overridden by CPU-specific code above.
314 * ANSI C requires that the following equations be true:
316 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
317 * sizeof(float) <= sizeof(double)
318 * CPU_BITS_PER_CHAR >= 8
319 * CPU_BITS_PER_SHORT >= 8
320 * CPU_BITS_PER_INT >= 16
321 * CPU_BITS_PER_LONG >= 32
326 #define SIZEOF_CHAR 1
330 #define SIZEOF_SHORT 2
334 #if CPU_REG_BITS < 32
339 #endif /* !SIZEOF_INT */
342 #if CPU_REG_BITS > 32
343 #define SIZEOF_LONG 8
345 #define SIZEOF_LONG 4
350 #define SIZEOF_PTR SIZEOF_INT
353 #ifndef CPU_BITS_PER_CHAR
354 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
357 #ifndef CPU_BITS_PER_SHORT
358 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
361 #ifndef CPU_BITS_PER_INT
362 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
365 #ifndef CPU_BITS_PER_LONG
366 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
369 #ifndef CPU_BITS_PER_PTR
370 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
374 /* Sanity checks for the above definitions */
375 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
376 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
377 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
378 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
384 * \brief Invoked by the scheduler to stop the CPU when idle.
386 * This hook can be redefined to put the CPU in low-power mode, or to
387 * profile system load with an external strobe, or to save CPU cycles
388 * in hosted environments such as emulators.
391 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
392 /* This emulator hook should yield the CPU to the host. */
394 void SchedulerIdle(void);
396 #define CPU_IDLE SchedulerIdle()
397 #else /* !ARCH_EMUL */
398 #define CPU_IDLE do { /* nothing */ } while (0)
399 #endif /* !ARCH_EMUL */
400 #endif /* !CPU_IDLE */
403 #define SCHEDULER_IDLE CPU_IDLE
405 #endif /* DEVLIB_CPU_H */