4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
18 * Revision 1.3 2004/07/18 21:49:51 bernie
21 * Revision 1.2 2004/06/03 11:27:09 bernie
22 * Add dual-license information.
24 * Revision 1.1 2004/05/23 17:48:35 bernie
25 * Add top-level files.
33 //! Initialization value for registers in stack frame
34 #define CPU_REG_INIT_VALUE(reg) 0
36 #if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__) /* 80C196 */
38 #define DISABLE_INTS disable_interrupt()
39 #define ENABLE_INTS enable_interrupt()
40 #define NOP nop_instruction()
41 #define SCHEDULER_IDLE /* Hmmm... could we go in STOP mode? */
43 typedef uint16_t cpuflags_t; // FIXME
44 typedef unsigned int cpustack_t;
46 #define CPU_REGS_CNT 16
47 #define CPU_STACK_GROWS_UPWARD 0
48 #define CPU_SP_ON_EMPTY_SLOT 0
50 #elif defined(__i386__) || defined(_MSC_VER) /* x86 */
52 #define NOP asm volatile ("nop")
53 #define DISABLE_INTS /* nothing */
54 #define ENABLE_INTS /* nothing */
55 #define SCHEDULER_IDLE SchedulerIdle()
57 typedef uint32_t cpuflags_t; // FIXME
58 typedef uint32_t cpustack_t;
60 #define CPU_REGS_CNT 7
61 #define CPU_STACK_GROWS_UPWARD 0
62 #define CPU_SP_ON_EMPTY_SLOT 0
64 #elif defined(__m56800E__) || defined(__m56800__) /* DSP56K */
67 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
68 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
69 #define SCHEDULER_IDLE /* nothing */
71 #define DISABLE_IRQSAVE(x) \
72 do { asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
73 #define ENABLE_IRQRESTORE(x) \
74 do { asm(move x,SR); } while (0)
76 typedef uint16_t cpuflags_t;
77 typedef unsigned int cpustack_t;
79 #define CPU_REGS_CNT FIXME
80 #define CPU_SAVED_REGS_CNT 28
81 #define CPU_STACK_GROWS_UPWARD 1
82 #define CPU_SP_ON_EMPTY_SLOT 0
84 #undef CPU_REG_INIT_VALUE
85 INLINE uint16_t CPU_REG_INIT_VALUE(int reg)
90 asm(move OMR, omr_img);
91 return omr_img & (BV(3)/*EX*/ | BV(1)/*MB*/ | BV(0)/*MA*/);
93 else if (reg == 16)/*M01*/
98 #elif defined (__AVR__)
100 #define NOP asm volatile ("nop" ::)
101 #define DISABLE_INTS asm volatile ("cli" ::)
102 #define ENABLE_INTS asm volatile ("sei" ::)
103 #define SCHEDULER_IDLE /* nothing */
105 #define DISABLE_IRQSAVE(x) \
107 __asm__ __volatile__( \
108 "in %0,__SREG__\n\t" \
110 : "=r" (x) : /* no inputs */ : "cc" \
114 #define ENABLE_IRQRESTORE(x) \
116 __asm__ __volatile__( \
117 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
121 typedef uint8_t cpuflags_t;
122 typedef uint8_t cpustack_t;
124 #define CPU_REGS_CNT 32
125 #define CPU_SAVED_REGS_CNT 18
126 #define CPU_STACK_GROWS_UPWARD 0
127 #define CPU_SP_ON_EMPTY_SLOT 1
134 #ifndef CPU_STACK_GROWS_UPWARD
135 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
138 #ifndef CPU_SP_ON_EMPTY_SLOT
139 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
143 * Support stack handling peculiarities of a few CPUs.
145 * Most processors let their stack grow downward and
146 * keep SP pointing at the last pushed value.
148 #if !CPU_STACK_GROWS_UPWARD
149 #if !CPU_SP_ON_EMPTY_SLOT
150 /* Most microprocessors (x86, m68k...) */
151 #define CPU_PUSH_WORD(sp, data) \
152 do { *--(sp) = (data); } while (0)
153 #define CPU_POP_WORD(sp) \
157 #define CPU_PUSH_WORD(sp, data) \
158 do { *(sp)-- = (data); } while (0)
159 #define CPU_POP_WORD(sp) \
163 #else /* CPU_STACK_GROWS_UPWARD */
165 #if !CPU_SP_ON_EMPTY_SLOT
166 /* DSP56K and other weirdos */
167 #define CPU_PUSH_WORD(sp, data) \
168 do { *++(sp) = (cpustack_t)(data); } while (0)
169 #define CPU_POP_WORD(sp) \
172 #error I bet you cannot find a CPU like this
177 #if defined(__m56800E__) || defined(__m56800__)
178 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
179 * RTS discards SR while returning (it does not restore it). So we push
180 * 0 to fake the same context.
182 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
184 CPU_PUSH_WORD((sp), (func)); \
185 CPU_PUSH_WORD((sp), 0); \
188 #elif defined (__AVR__)
189 /* In AVR, the addresses are pushed into the stack as little-endian, while
190 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
191 * no natural endianess).
193 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
195 uint16_t funcaddr = (uint16_t)(func); \
196 CPU_PUSH_WORD((sp), funcaddr); \
197 CPU_PUSH_WORD((sp), funcaddr>>8); \
201 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
202 CPU_PUSH_WORD((sp), (func))