4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.23 2004/11/16 22:41:58 bernie
21 *#* Support 64bit CPUs.
23 *#* Revision 1.22 2004/11/16 21:57:59 bernie
24 *#* CPU_IDLE: Rename from SCHEDULER_IDLE.
26 *#* Revision 1.21 2004/11/16 21:34:25 bernie
27 *#* Commonize obsolete names for IRQ macros; Doxygen fixes.
29 *#* Revision 1.20 2004/11/16 20:33:32 bernie
30 *#* CPU_HARVARD: New macro.
32 *#* Revision 1.19 2004/10/03 20:43:54 bernie
33 *#* Fix Doxygen markup.
35 *#* Revision 1.18 2004/10/03 18:36:31 bernie
36 *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
38 *#* Revision 1.17 2004/09/06 21:48:27 bernie
39 *#* ATOMIC(): New macro.
41 *#* Revision 1.16 2004/08/29 21:58:33 bernie
42 *#* Rename BITS_PER_XYZ macros; Add sanity checks.
44 *#* Revision 1.15 2004/08/25 14:12:08 rasky
45 *#* Aggiornato il comment block dei log RCS
47 *#* Revision 1.14 2004/08/24 13:29:28 bernie
48 *#* Trim CVS log; Rename header guards.
50 *#* Revision 1.12 2004/08/14 19:37:57 rasky
51 *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
53 *#* Revision 1.11 2004/08/05 17:39:56 bernie
54 *#* Fix a Doxygen tag.
56 *#* Revision 1.10 2004/08/02 20:20:29 aleph
57 *#* Merge from project_ks
59 *#* Revision 1.9 2004/07/30 14:24:16 rasky
60 *#* Task switching con salvataggio perfetto stato di interrupt (SR)
61 *#* Kernel monitor per dump informazioni su stack dei processi
66 #include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
70 * \name Macros for determining CPU endianness.
73 #define CPU_BIG_ENDIAN 0x1234
74 #define CPU_LITTLE_ENDIAN 0x3412
77 /*! Macro to include cpu-specific versions of the headers. */
78 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
83 #define NOP nop_instruction()
84 #define IRQ_DISABLE disable_interrupt()
85 #define IRQ_ENABLE enable_interrupt()
87 typedef uint16_t cpuflags_t; // FIXME
88 typedef unsigned int cpustack_t;
90 #define CPU_REG_BITS 16
91 #define CPU_REGS_CNT 16
92 #define CPU_STACK_GROWS_UPWARD 0
93 #define CPU_SP_ON_EMPTY_SLOT 0
94 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
99 #define NOP asm volatile ("nop")
100 #define IRQ_DISABLE /* nothing */
101 #define IRQ_ENABLE /* nothing */
103 typedef uint32_t cpuflags_t; // FIXME
104 typedef uint32_t cpustack_t;
106 #define CPU_REG_BITS 32
107 #define CPU_REGS_CNT 7
108 #define CPU_STACK_GROWS_UPWARD 0
109 #define CPU_SP_ON_EMPTY_SLOT 0
110 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
111 #define CPU_HARVARD 0
116 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
117 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
119 #define IRQ_SAVE_DISABLE(x) \
120 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
121 #define IRQ_RESTORE(x) \
122 do { (void)x; asm(move x,SR); } while (0)
125 typedef uint16_t cpuflags_t;
126 typedef unsigned int cpustack_t;
128 #define CPU_REG_BITS 16
129 #define CPU_REGS_CNT FIXME
130 #define CPU_SAVED_REGS_CNT 8
131 #define CPU_STACK_GROWS_UPWARD 1
132 #define CPU_SP_ON_EMPTY_SLOT 0
133 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
135 /* Memory is word-addessed in the DSP56K */
136 #define CPU_BITS_PER_CHAR 16
137 #define SIZEOF_SHORT 1
139 #define SIZEOF_LONG 2
144 #define NOP asm volatile ("nop" ::)
145 #define IRQ_DISABLE asm volatile ("cli" ::)
146 #define IRQ_ENABLE asm volatile ("sei" ::)
148 #define IRQ_SAVE_DISABLE(x) \
150 __asm__ __volatile__( \
151 "in %0,__SREG__\n\t" \
153 : "=r" (x) : /* no inputs */ : "cc" \
157 #define IRQ_RESTORE(x) \
159 __asm__ __volatile__( \
160 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
164 #define IRQ_GETSTATE() \
167 __asm__ __volatile__( \
168 "in %0,__SREG__\n\t" \
169 : "=r" (sreg) /* no inputs & no clobbers */ \
171 (bool)(sreg & 0x80); \
174 typedef uint8_t cpuflags_t;
175 typedef uint8_t cpustack_t;
177 /* Register counts include SREG too */
178 #define CPU_REG_BITS 8
179 #define CPU_REGS_CNT 33
180 #define CPU_SAVED_REGS_CNT 19
181 #define CPU_STACK_GROWS_UPWARD 0
182 #define CPU_SP_ON_EMPTY_SLOT 1
183 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
186 * Initialization value for registers in stack frame.
187 * The register index is not directly corrispondent to CPU
188 * register numbers. Index 0 is the SREG register: the initial
189 * value is all 0 but the interrupt bit (bit 7).
191 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
196 #define DISABLE_INTS IRQ_DISABLE
197 #define ENABLE_INTS IRQ_ENABLE
198 #define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x)
199 #define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
202 * Execute \a CODE atomically with respect to interrupts.
204 * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
206 #define ATOMIC(CODE) \
208 cpuflags_t __flags; \
209 DISABLE_IRQSAVE(__flags); \
211 ENABLE_IRQRESTORE(__flags); \
215 //! Default for macro not defined in the right arch section
216 #ifndef CPU_REG_INIT_VALUE
217 #define CPU_REG_INIT_VALUE(reg) 0
221 #ifndef CPU_STACK_GROWS_UPWARD
222 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
225 #ifndef CPU_SP_ON_EMPTY_SLOT
226 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
230 * Support stack handling peculiarities of a few CPUs.
232 * Most processors let their stack grow downward and
233 * keep SP pointing at the last pushed value.
235 #if !CPU_STACK_GROWS_UPWARD
236 #if !CPU_SP_ON_EMPTY_SLOT
237 /* Most microprocessors (x86, m68k...) */
238 #define CPU_PUSH_WORD(sp, data) \
239 do { *--(sp) = (data); } while (0)
240 #define CPU_POP_WORD(sp) \
244 #define CPU_PUSH_WORD(sp, data) \
245 do { *(sp)-- = (data); } while (0)
246 #define CPU_POP_WORD(sp) \
250 #else /* CPU_STACK_GROWS_UPWARD */
252 #if !CPU_SP_ON_EMPTY_SLOT
253 /* DSP56K and other weirdos */
254 #define CPU_PUSH_WORD(sp, data) \
255 do { *++(sp) = (cpustack_t)(data); } while (0)
256 #define CPU_POP_WORD(sp) \
259 #error I bet you cannot find a CPU like this
266 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
267 * RTS discards SR while returning (it does not restore it). So we push
268 * 0 to fake the same context.
270 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
272 CPU_PUSH_WORD((sp), (func)); \
273 CPU_PUSH_WORD((sp), 0x100); \
278 * In AVR, the addresses are pushed into the stack as little-endian, while
279 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
280 * no natural endianess).
282 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
284 uint16_t funcaddr = (uint16_t)(func); \
285 CPU_PUSH_WORD((sp), funcaddr); \
286 CPU_PUSH_WORD((sp), funcaddr>>8); \
290 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
291 CPU_PUSH_WORD((sp), (func))
296 * \name Default type sizes
298 * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
299 * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
300 * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
302 * These defaults are reasonable for most 16/32bit machines.
303 * Some of these macros may be overridden by CPU-specific code above.
305 * ANSI C requires that the following equations be true:
307 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
308 * sizeof(float) <= sizeof(double)
309 * CPU_BITS_PER_CHAR >= 8
310 * CPU_BITS_PER_SHORT >= 8
311 * CPU_BITS_PER_INT >= 16
312 * CPU_BITS_PER_LONG >= 32
317 #define SIZEOF_CHAR 1
321 #define SIZEOF_SHORT 2
325 #if CPU_REG_BITS < 32
330 #endif /* !SIZEOF_INT */
333 #if CPU_REG_BITS > 32
334 #define SIZEOF_LONG 8
336 #define SIZEOF_LONG 4
341 #define SIZEOF_PTR SIZEOF_INT
344 #ifndef CPU_BITS_PER_CHAR
345 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
348 #ifndef CPU_BITS_PER_SHORT
349 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
352 #ifndef CPU_BITS_PER_INT
353 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
356 #ifndef CPU_BITS_PER_LONG
357 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
360 #ifndef CPU_BITS_PER_PTR
361 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
365 /* Sanity checks for the above definitions */
366 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
367 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
368 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
369 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
373 * \def SCHEDULER_IDLE
375 * \brief Invoked by the scheduler to stop the CPU when idle.
377 * This hook can be redefined to put the CPU in low-power mode, or to
378 * profile system load with an external strobe, or to save CPU cycles
379 * in hosted environments such as emulators.
382 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
383 /* This emulator hook should yield the CPU to the host. */
385 void SchedulerIdle(void);
387 #define CPU_IDLE SchedulerIdle()
388 #else /* !ARCH_EMUL */
389 #define CPU_IDLE do { /* nothing */ } while (0)
390 #endif /* !ARCH_EMUL */
391 #endif /* !CPU_IDLE */
394 #define SCHEDULER_IDLE CPU_IDLE
396 #endif /* DEVLIB_CPU_H */