4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 * Revision 1.5 2004/07/20 16:20:35 bernie
21 * Move byte-order macros to mware/byteorder.h; Add missing author names.
23 * Revision 1.4 2004/07/20 16:06:04 bernie
24 * Add macros to handle endianess issues.
26 * Revision 1.3 2004/07/18 21:49:51 bernie
29 * Revision 1.2 2004/06/03 11:27:09 bernie
30 * Add dual-license information.
32 * Revision 1.1 2004/05/23 17:48:35 bernie
33 * Add top-level files.
41 //! Initialization value for registers in stack frame
42 #define CPU_REG_INIT_VALUE(reg) 0
44 // Macros for determining CPU endianness
45 #define CPU_BIG_ENDIAN 0x1234
46 #define CPU_LITTLE_ENDIAN 0x3412
49 #if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__) /* 80C196 */
51 #define DISABLE_INTS disable_interrupt()
52 #define ENABLE_INTS enable_interrupt()
53 #define NOP nop_instruction()
54 #define SCHEDULER_IDLE /* Hmmm... could we go in STOP mode? */
56 typedef uint16_t cpuflags_t; // FIXME
57 typedef unsigned int cpustack_t;
59 #define CPU_REGS_CNT 16
60 #define CPU_STACK_GROWS_UPWARD 0
61 #define CPU_SP_ON_EMPTY_SLOT 0
62 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
64 #elif defined(__i386__) || defined(_MSC_VER) /* x86 */
66 #define NOP asm volatile ("nop")
67 #define DISABLE_INTS /* nothing */
68 #define ENABLE_INTS /* nothing */
69 #define SCHEDULER_IDLE SchedulerIdle()
71 typedef uint32_t cpuflags_t; // FIXME
72 typedef uint32_t cpustack_t;
74 #define CPU_REGS_CNT 7
75 #define CPU_STACK_GROWS_UPWARD 0
76 #define CPU_SP_ON_EMPTY_SLOT 0
77 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
79 #elif defined(__m56800E__) || defined(__m56800__) /* DSP56K */
82 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
83 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
84 #define SCHEDULER_IDLE /* nothing */
86 #define DISABLE_IRQSAVE(x) \
87 do { asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
88 #define ENABLE_IRQRESTORE(x) \
89 do { asm(move x,SR); } while (0)
91 typedef uint16_t cpuflags_t;
92 typedef unsigned int cpustack_t;
94 #define CPU_REGS_CNT FIXME
95 #define CPU_SAVED_REGS_CNT 28
96 #define CPU_STACK_GROWS_UPWARD 1
97 #define CPU_SP_ON_EMPTY_SLOT 0
98 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
100 #undef CPU_REG_INIT_VALUE
101 INLINE uint16_t CPU_REG_INIT_VALUE(int reg)
106 asm(move OMR, omr_img);
107 return omr_img & (BV(3)/*EX*/ | BV(1)/*MB*/ | BV(0)/*MA*/);
109 else if (reg == 16)/*M01*/
114 #elif defined (__AVR__)
116 #define NOP asm volatile ("nop" ::)
117 #define DISABLE_INTS asm volatile ("cli" ::)
118 #define ENABLE_INTS asm volatile ("sei" ::)
119 #define SCHEDULER_IDLE /* nothing */
121 #define DISABLE_IRQSAVE(x) \
123 __asm__ __volatile__( \
124 "in %0,__SREG__\n\t" \
126 : "=r" (x) : /* no inputs */ : "cc" \
130 #define ENABLE_IRQRESTORE(x) \
132 __asm__ __volatile__( \
133 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
137 typedef uint8_t cpuflags_t;
138 typedef uint8_t cpustack_t;
140 #define CPU_REGS_CNT 32
141 #define CPU_SAVED_REGS_CNT 18
142 #define CPU_STACK_GROWS_UPWARD 0
143 #define CPU_SP_ON_EMPTY_SLOT 1
144 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
150 #ifndef CPU_STACK_GROWS_UPWARD
151 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
154 #ifndef CPU_SP_ON_EMPTY_SLOT
155 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
159 * Support stack handling peculiarities of a few CPUs.
161 * Most processors let their stack grow downward and
162 * keep SP pointing at the last pushed value.
164 #if !CPU_STACK_GROWS_UPWARD
165 #if !CPU_SP_ON_EMPTY_SLOT
166 /* Most microprocessors (x86, m68k...) */
167 #define CPU_PUSH_WORD(sp, data) \
168 do { *--(sp) = (data); } while (0)
169 #define CPU_POP_WORD(sp) \
173 #define CPU_PUSH_WORD(sp, data) \
174 do { *(sp)-- = (data); } while (0)
175 #define CPU_POP_WORD(sp) \
179 #else /* CPU_STACK_GROWS_UPWARD */
181 #if !CPU_SP_ON_EMPTY_SLOT
182 /* DSP56K and other weirdos */
183 #define CPU_PUSH_WORD(sp, data) \
184 do { *++(sp) = (cpustack_t)(data); } while (0)
185 #define CPU_POP_WORD(sp) \
188 #error I bet you cannot find a CPU like this
193 #if defined(__m56800E__) || defined(__m56800__)
194 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
195 * RTS discards SR while returning (it does not restore it). So we push
196 * 0 to fake the same context.
198 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
200 CPU_PUSH_WORD((sp), (func)); \
201 CPU_PUSH_WORD((sp), 0); \
204 #elif defined (__AVR__)
205 /* In AVR, the addresses are pushed into the stack as little-endian, while
206 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
207 * no natural endianess).
209 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
211 uint16_t funcaddr = (uint16_t)(func); \
212 CPU_PUSH_WORD((sp), funcaddr); \
213 CPU_PUSH_WORD((sp), funcaddr>>8); \
217 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
218 CPU_PUSH_WORD((sp), (func))