4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.17 2004/09/06 21:48:27 bernie
21 *#* ATOMIC(): New macro.
23 *#* Revision 1.16 2004/08/29 21:58:33 bernie
24 *#* Rename BITS_PER_XYZ macros; Add sanity checks.
26 *#* Revision 1.15 2004/08/25 14:12:08 rasky
27 *#* Aggiornato il comment block dei log RCS
29 *#* Revision 1.14 2004/08/24 13:29:28 bernie
30 *#* Trim CVS log; Rename header guards.
32 *#* Revision 1.12 2004/08/14 19:37:57 rasky
33 *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
35 *#* Revision 1.11 2004/08/05 17:39:56 bernie
36 *#* Fix a Doxygen tag.
38 *#* Revision 1.10 2004/08/02 20:20:29 aleph
39 *#* Merge from project_ks
41 *#* Revision 1.9 2004/07/30 14:24:16 rasky
42 *#* Task switching con salvataggio perfetto stato di interrupt (SR)
43 *#* Kernel monitor per dump informazioni su stack dei processi
48 #include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
51 // Macros for determining CPU endianness
52 #define CPU_BIG_ENDIAN 0x1234
53 #define CPU_LITTLE_ENDIAN 0x3412
55 // Macros to include cpu-specific version of the headers
56 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
61 #define DISABLE_INTS disable_interrupt()
62 #define ENABLE_INTS enable_interrupt()
63 #define NOP nop_instruction()
65 typedef uint16_t cpuflags_t; // FIXME
66 typedef unsigned int cpustack_t;
68 #define CPU_REG_BITS 16
69 #define CPU_REGS_CNT 16
70 #define CPU_STACK_GROWS_UPWARD 0
71 #define CPU_SP_ON_EMPTY_SLOT 0
72 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
76 #define NOP asm volatile ("nop")
77 #define DISABLE_INTS /* nothing */
78 #define ENABLE_INTS /* nothing */
80 typedef uint32_t cpuflags_t; // FIXME
81 typedef uint32_t cpustack_t;
83 #define CPU_REG_BITS 32
84 #define CPU_REGS_CNT 7
85 #define CPU_STACK_GROWS_UPWARD 0
86 #define CPU_SP_ON_EMPTY_SLOT 0
87 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
92 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
93 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
95 #define DISABLE_IRQSAVE(x) \
96 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
97 #define ENABLE_IRQRESTORE(x) \
98 do { (void)x; asm(move x,SR); } while (0)
100 typedef uint16_t cpuflags_t;
101 typedef unsigned int cpustack_t;
103 #define CPU_REG_BITS 16
104 #define CPU_REGS_CNT FIXME
105 #define CPU_SAVED_REGS_CNT 8
106 #define CPU_STACK_GROWS_UPWARD 1
107 #define CPU_SP_ON_EMPTY_SLOT 0
108 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
110 /* Memory is word-addessed in the DSP56K */
111 #define CPU_BITS_PER_CHAR 16
112 #define SIZEOF_SHORT 1
114 #define SIZEOF_LONG 2
119 #define NOP asm volatile ("nop" ::)
120 #define DISABLE_INTS asm volatile ("cli" ::)
121 #define ENABLE_INTS asm volatile ("sei" ::)
123 #define DISABLE_IRQSAVE(x) \
125 __asm__ __volatile__( \
126 "in %0,__SREG__\n\t" \
128 : "=r" (x) : /* no inputs */ : "cc" \
132 #define ENABLE_IRQRESTORE(x) \
134 __asm__ __volatile__( \
135 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
139 typedef uint8_t cpuflags_t;
140 typedef uint8_t cpustack_t;
142 /* Register counts include SREG too */
143 #define CPU_REG_BITS 8
144 #define CPU_REGS_CNT 33
145 #define CPU_SAVED_REGS_CNT 19
146 #define CPU_STACK_GROWS_UPWARD 0
147 #define CPU_SP_ON_EMPTY_SLOT 1
148 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
151 * Initialization value for registers in stack frame.
152 * The register index is not directly corrispondent to CPU
153 * register numbers. Index 0 is the SREG register: the initial
154 * value is all 0 but the interrupt bit (bit 7).
156 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
161 * Execute \a CODE atomically with respect to interrupts.
163 * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
165 #define ATOMIC(CODE) \
167 cpuflags_t __flags; \
168 DISABLE_IRQSAVE(__flags); \
170 ENABLE_IRQRESTORE(__flags); \
174 //! Default for macro not defined in the right arch section
175 #ifndef CPU_REG_INIT_VALUE
176 #define CPU_REG_INIT_VALUE(reg) 0
180 #ifndef CPU_STACK_GROWS_UPWARD
181 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
184 #ifndef CPU_SP_ON_EMPTY_SLOT
185 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
189 * Support stack handling peculiarities of a few CPUs.
191 * Most processors let their stack grow downward and
192 * keep SP pointing at the last pushed value.
194 #if !CPU_STACK_GROWS_UPWARD
195 #if !CPU_SP_ON_EMPTY_SLOT
196 /* Most microprocessors (x86, m68k...) */
197 #define CPU_PUSH_WORD(sp, data) \
198 do { *--(sp) = (data); } while (0)
199 #define CPU_POP_WORD(sp) \
203 #define CPU_PUSH_WORD(sp, data) \
204 do { *(sp)-- = (data); } while (0)
205 #define CPU_POP_WORD(sp) \
209 #else /* CPU_STACK_GROWS_UPWARD */
211 #if !CPU_SP_ON_EMPTY_SLOT
212 /* DSP56K and other weirdos */
213 #define CPU_PUSH_WORD(sp, data) \
214 do { *++(sp) = (cpustack_t)(data); } while (0)
215 #define CPU_POP_WORD(sp) \
218 #error I bet you cannot find a CPU like this
224 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
225 * RTS discards SR while returning (it does not restore it). So we push
226 * 0 to fake the same context.
228 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
230 CPU_PUSH_WORD((sp), (func)); \
231 CPU_PUSH_WORD((sp), 0x100); \
235 /* In AVR, the addresses are pushed into the stack as little-endian, while
236 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
237 * no natural endianess).
239 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
241 uint16_t funcaddr = (uint16_t)(func); \
242 CPU_PUSH_WORD((sp), funcaddr); \
243 CPU_PUSH_WORD((sp), funcaddr>>8); \
247 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
248 CPU_PUSH_WORD((sp), (func))
253 * \name Default type sizes
255 * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
256 * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
257 * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
259 * These defaults are reasonable for most 16/32bit machines.
260 * Some of these macros may be overridden by CPU-specific code above.
262 * ANSI C requires that the following equations be true:
264 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
265 * sizeof(float) <= sizeof(double)
266 * CPU_BITS_PER_CHAR >= 8
267 * CPU_BITS_PER_SHORT >= 8
268 * CPU_BITS_PER_INT >= 16
269 * CPU_BITS_PER_LONG >= 32
274 #define SIZEOF_CHAR 1
278 #define SIZEOF_SHORT 2
282 #if CPU_REG_BITS < 32
287 #endif /* !SIZEOF_INT */
290 #define SIZEOF_LONG 4
294 #define SIZEOF_PTR SIZEOF_INT
297 #ifndef CPU_BITS_PER_CHAR
298 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
301 #ifndef CPU_BITS_PER_SHORT
302 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
305 #ifndef CPU_BITS_PER_INT
306 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
309 #ifndef CPU_BITS_PER_LONG
310 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
313 #ifndef CPU_BITS_PER_PTR
314 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
318 /* Sanity checks for the above definitions */
319 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
320 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
321 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
322 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
326 * \def SCHEDULER_IDLE
328 * \brief Invoked by the scheduler to stop the CPU when idle.
330 * This hook can be redefined to put the CPU in low-power mode, or to
331 * profile system load with an external strobe, or to save CPU cycles
332 * in hosted environments such as emulators.
334 #ifndef SCHEDULER_IDLE
335 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
336 /* This emulator hook should yield the CPU to the host. */
338 void SchedulerIdle(void);
340 #define SCHEDULER_IDLE SchedulerIdle()
341 #else /* !ARCH_EMUL */
342 #define SCHEDULER_IDLE do { /* nothing */ } while (0)
343 #endif /* !ARCH_EMUL */
344 #endif /* !SCHEDULER_IDLE */
346 #endif /* DEVLIB_CPU_H */