4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.22 2004/11/16 21:57:59 bernie
21 *#* CPU_IDLE: Rename from SCHEDULER_IDLE.
23 *#* Revision 1.21 2004/11/16 21:34:25 bernie
24 *#* Commonize obsolete names for IRQ macros; Doxygen fixes.
26 *#* Revision 1.20 2004/11/16 20:33:32 bernie
27 *#* CPU_HARVARD: New macro.
29 *#* Revision 1.19 2004/10/03 20:43:54 bernie
30 *#* Fix Doxygen markup.
32 *#* Revision 1.18 2004/10/03 18:36:31 bernie
33 *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
35 *#* Revision 1.17 2004/09/06 21:48:27 bernie
36 *#* ATOMIC(): New macro.
38 *#* Revision 1.16 2004/08/29 21:58:33 bernie
39 *#* Rename BITS_PER_XYZ macros; Add sanity checks.
41 *#* Revision 1.15 2004/08/25 14:12:08 rasky
42 *#* Aggiornato il comment block dei log RCS
44 *#* Revision 1.14 2004/08/24 13:29:28 bernie
45 *#* Trim CVS log; Rename header guards.
47 *#* Revision 1.12 2004/08/14 19:37:57 rasky
48 *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
50 *#* Revision 1.11 2004/08/05 17:39:56 bernie
51 *#* Fix a Doxygen tag.
53 *#* Revision 1.10 2004/08/02 20:20:29 aleph
54 *#* Merge from project_ks
56 *#* Revision 1.9 2004/07/30 14:24:16 rasky
57 *#* Task switching con salvataggio perfetto stato di interrupt (SR)
58 *#* Kernel monitor per dump informazioni su stack dei processi
63 #include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
67 * \name Macros for determining CPU endianness.
70 #define CPU_BIG_ENDIAN 0x1234
71 #define CPU_LITTLE_ENDIAN 0x3412
74 /*! Macro to include cpu-specific versions of the headers. */
75 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
80 #define NOP nop_instruction()
81 #define IRQ_DISABLE disable_interrupt()
82 #define IRQ_ENABLE enable_interrupt()
84 typedef uint16_t cpuflags_t; // FIXME
85 typedef unsigned int cpustack_t;
87 #define CPU_REG_BITS 16
88 #define CPU_REGS_CNT 16
89 #define CPU_STACK_GROWS_UPWARD 0
90 #define CPU_SP_ON_EMPTY_SLOT 0
91 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
96 #define NOP asm volatile ("nop")
97 #define IRQ_DISABLE /* nothing */
98 #define IRQ_ENABLE /* nothing */
100 typedef uint32_t cpuflags_t; // FIXME
101 typedef uint32_t cpustack_t;
103 #define CPU_REG_BITS 32
104 #define CPU_REGS_CNT 7
105 #define CPU_STACK_GROWS_UPWARD 0
106 #define CPU_SP_ON_EMPTY_SLOT 0
107 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
108 #define CPU_HARVARD 0
113 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
114 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
116 #define IRQ_SAVE_DISABLE(x) \
117 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
118 #define IRQ_RESTORE(x) \
119 do { (void)x; asm(move x,SR); } while (0)
122 typedef uint16_t cpuflags_t;
123 typedef unsigned int cpustack_t;
125 #define CPU_REG_BITS 16
126 #define CPU_REGS_CNT FIXME
127 #define CPU_SAVED_REGS_CNT 8
128 #define CPU_STACK_GROWS_UPWARD 1
129 #define CPU_SP_ON_EMPTY_SLOT 0
130 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
132 /* Memory is word-addessed in the DSP56K */
133 #define CPU_BITS_PER_CHAR 16
134 #define SIZEOF_SHORT 1
136 #define SIZEOF_LONG 2
141 #define NOP asm volatile ("nop" ::)
142 #define IRQ_DISABLE asm volatile ("cli" ::)
143 #define IRQ_ENABLE asm volatile ("sei" ::)
145 #define IRQ_SAVE_DISABLE(x) \
147 __asm__ __volatile__( \
148 "in %0,__SREG__\n\t" \
150 : "=r" (x) : /* no inputs */ : "cc" \
154 #define IRQ_RESTORE(x) \
156 __asm__ __volatile__( \
157 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
161 #define IRQ_GETSTATE() \
164 __asm__ __volatile__( \
165 "in %0,__SREG__\n\t" \
166 : "=r" (sreg) /* no inputs & no clobbers */ \
168 (bool)(sreg & 0x80); \
171 typedef uint8_t cpuflags_t;
172 typedef uint8_t cpustack_t;
174 /* Register counts include SREG too */
175 #define CPU_REG_BITS 8
176 #define CPU_REGS_CNT 33
177 #define CPU_SAVED_REGS_CNT 19
178 #define CPU_STACK_GROWS_UPWARD 0
179 #define CPU_SP_ON_EMPTY_SLOT 1
180 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
183 * Initialization value for registers in stack frame.
184 * The register index is not directly corrispondent to CPU
185 * register numbers. Index 0 is the SREG register: the initial
186 * value is all 0 but the interrupt bit (bit 7).
188 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
193 #define DISABLE_INTS IRQ_DISABLE
194 #define ENABLE_INTS IRQ_ENABLE
195 #define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x)
196 #define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
199 * Execute \a CODE atomically with respect to interrupts.
201 * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
203 #define ATOMIC(CODE) \
205 cpuflags_t __flags; \
206 DISABLE_IRQSAVE(__flags); \
208 ENABLE_IRQRESTORE(__flags); \
212 //! Default for macro not defined in the right arch section
213 #ifndef CPU_REG_INIT_VALUE
214 #define CPU_REG_INIT_VALUE(reg) 0
218 #ifndef CPU_STACK_GROWS_UPWARD
219 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
222 #ifndef CPU_SP_ON_EMPTY_SLOT
223 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
227 * Support stack handling peculiarities of a few CPUs.
229 * Most processors let their stack grow downward and
230 * keep SP pointing at the last pushed value.
232 #if !CPU_STACK_GROWS_UPWARD
233 #if !CPU_SP_ON_EMPTY_SLOT
234 /* Most microprocessors (x86, m68k...) */
235 #define CPU_PUSH_WORD(sp, data) \
236 do { *--(sp) = (data); } while (0)
237 #define CPU_POP_WORD(sp) \
241 #define CPU_PUSH_WORD(sp, data) \
242 do { *(sp)-- = (data); } while (0)
243 #define CPU_POP_WORD(sp) \
247 #else /* CPU_STACK_GROWS_UPWARD */
249 #if !CPU_SP_ON_EMPTY_SLOT
250 /* DSP56K and other weirdos */
251 #define CPU_PUSH_WORD(sp, data) \
252 do { *++(sp) = (cpustack_t)(data); } while (0)
253 #define CPU_POP_WORD(sp) \
256 #error I bet you cannot find a CPU like this
263 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
264 * RTS discards SR while returning (it does not restore it). So we push
265 * 0 to fake the same context.
267 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
269 CPU_PUSH_WORD((sp), (func)); \
270 CPU_PUSH_WORD((sp), 0x100); \
275 * In AVR, the addresses are pushed into the stack as little-endian, while
276 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
277 * no natural endianess).
279 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
281 uint16_t funcaddr = (uint16_t)(func); \
282 CPU_PUSH_WORD((sp), funcaddr); \
283 CPU_PUSH_WORD((sp), funcaddr>>8); \
287 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
288 CPU_PUSH_WORD((sp), (func))
293 * \name Default type sizes
295 * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
296 * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
297 * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
299 * These defaults are reasonable for most 16/32bit machines.
300 * Some of these macros may be overridden by CPU-specific code above.
302 * ANSI C requires that the following equations be true:
304 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
305 * sizeof(float) <= sizeof(double)
306 * CPU_BITS_PER_CHAR >= 8
307 * CPU_BITS_PER_SHORT >= 8
308 * CPU_BITS_PER_INT >= 16
309 * CPU_BITS_PER_LONG >= 32
314 #define SIZEOF_CHAR 1
318 #define SIZEOF_SHORT 2
322 #if CPU_REG_BITS < 32
327 #endif /* !SIZEOF_INT */
330 #define SIZEOF_LONG 4
334 #define SIZEOF_PTR SIZEOF_INT
337 #ifndef CPU_BITS_PER_CHAR
338 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
341 #ifndef CPU_BITS_PER_SHORT
342 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
345 #ifndef CPU_BITS_PER_INT
346 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
349 #ifndef CPU_BITS_PER_LONG
350 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
353 #ifndef CPU_BITS_PER_PTR
354 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
358 /* Sanity checks for the above definitions */
359 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
360 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
361 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
362 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
366 * \def SCHEDULER_IDLE
368 * \brief Invoked by the scheduler to stop the CPU when idle.
370 * This hook can be redefined to put the CPU in low-power mode, or to
371 * profile system load with an external strobe, or to save CPU cycles
372 * in hosted environments such as emulators.
375 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
376 /* This emulator hook should yield the CPU to the host. */
378 void SchedulerIdle(void);
380 #define CPU_IDLE SchedulerIdle()
381 #else /* !ARCH_EMUL */
382 #define CPU_IDLE do { /* nothing */ } while (0)
383 #endif /* !ARCH_EMUL */
384 #endif /* !CPU_IDLE */
387 #define SCHEDULER_IDLE CPU_IDLE
389 #endif /* DEVLIB_CPU_H */