4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
18 * Revision 1.2 2004/06/03 11:27:09 bernie
19 * Add dual-license information.
21 * Revision 1.1 2004/05/23 17:48:35 bernie
22 * Add top-level files.
30 //! Initialization value for registers in stack frame
31 #define CPU_REG_INIT_VALUE(reg) 0
33 #if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__) /* 80C196 */
35 #define DISABLE_INTS disable_interrupt()
36 #define ENABLE_INTS enable_interrupt()
37 #define NOP nop_instruction()
38 #define SCHEDULER_IDLE /* Hmmm... could we go in STOP mode? */
40 typedef uint16_t cpuflags_t; // FIXME
41 typedef unsigned int cpustack_t;
43 #define CPU_REGS_CNT 16
44 #define CPU_STACK_GROWS_UPWARD 0
45 #define CPU_SP_ON_EMPTY_SLOT 0
47 #elif defined(__i386__) || defined(_MSC_VER) /* x86 */
49 #define NOP asm volatile ("nop")
50 #define DISABLE_INTS /* nothing */
51 #define ENABLE_INTS /* nothing */
52 #define SCHEDULER_IDLE SchedulerIdle()
54 typedef uint32_t cpuflags_t; // FIXME
55 typedef uint32_t cpustack_t;
57 #define CPU_REGS_CNT 7
58 #define CPU_STACK_GROWS_UPWARD 0
59 #define CPU_SP_ON_EMPTY_SLOT 0
61 #elif defined(__m56800E__) || defined(__m56800__) /* DSP56K */
64 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
65 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
66 #define SCHEDULER_IDLE /* nothing */
68 #define DISABLE_IRQSAVE(x) \
69 do { asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
70 #define ENABLE_IRQRESTORE(x) \
71 do { asm(move x,SR); } while (0)
73 typedef uint16_t cpuflags_t;
74 typedef unsigned int cpustack_t;
76 #define CPU_REGS_CNT FIXME
77 #define CPU_SAVED_REGS_CNT 28
78 #define CPU_STACK_GROWS_UPWARD 1
79 #define CPU_SP_ON_EMPTY_SLOT 0
81 #undef CPU_REG_INIT_VALUE
82 INLINE uint16_t CPU_REG_INIT_VALUE(int reg)
87 asm(move OMR, omr_img);
88 return omr_img & (BV(3)/*EX*/ | BV(1)/*MB*/ | BV(0)/*MA*/);
90 else if (reg == 16)/*M01*/
95 #elif defined (__AVR__)
97 #define NOP asm volatile ("nop")
98 #define DISABLE_INTS cli()
99 #define ENABLE_INTS sei()
100 #define SCHEDULER_IDLE /* nothing */
102 #define DISABLE_IRQSAVE(x) \
104 __asm__ __volatile__( \
105 "in %0,__SREG__\n\t" \
107 : "=r" (x) : /* no inputs */ : "cc" \
111 #define ENABLE_IRQRESTORE(x) \
113 __asm__ __volatile__( \
114 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
118 typedef uint8_t cpuflags_t;
119 typedef uint8_t cpustack_t;
121 #define CPU_REGS_CNT 32
122 #define CPU_SAVED_REGS_CNT 18
123 #define CPU_STACK_GROWS_UPWARD 0
124 #define CPU_SP_ON_EMPTY_SLOT 1
131 #ifndef CPU_STACK_GROWS_UPWARD
132 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
135 #ifndef CPU_SP_ON_EMPTY_SLOT
136 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
140 * Support stack handling peculiarities of a few CPUs.
142 * Most processors let their stack grow downward and
143 * keep SP pointing at the last pushed value.
145 #if !CPU_STACK_GROWS_UPWARD
146 #if !CPU_SP_ON_EMPTY_SLOT
147 /* Most microprocessors (x86, m68k...) */
148 #define CPU_PUSH_WORD(sp, data) \
149 do { *--(sp) = (data); } while (0)
150 #define CPU_POP_WORD(sp) \
154 #define CPU_PUSH_WORD(sp, data) \
155 do { *(sp)-- = (data); } while (0)
156 #define CPU_POP_WORD(sp) \
160 #else /* CPU_STACK_GROWS_UPWARD */
162 #if !CPU_SP_ON_EMPTY_SLOT
163 /* DSP56K and other weirdos */
164 #define CPU_PUSH_WORD(sp, data) \
165 do { *++(sp) = (cpustack_t)(data); } while (0)
166 #define CPU_POP_WORD(sp) \
169 #error I bet you cannot find a CPU like this
174 #if defined(__m56800E__) || defined(__m56800__)
175 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
176 * RTS discards SR while returning (it does not restore it). So we push
177 * 0 to fake the same context.
179 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
181 CPU_PUSH_WORD((sp), (func)); \
182 CPU_PUSH_WORD((sp), 0); \
185 #elif defined (__AVR__)
186 /* In AVR, the addresses are pushed into the stack as little-endian, while
187 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
188 * no natural endianess).
190 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
192 uint16_t funcaddr = (uint16_t)(func); \
193 CPU_PUSH_WORD((sp), funcaddr); \
194 CPU_PUSH_WORD((sp), funcaddr>>8); \
198 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
199 CPU_PUSH_WORD((sp), (func))