4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 * Revision 1.13 2004/08/24 13:16:00 bernie
21 * Add type-size definitions for preprocessor.
23 * Revision 1.12 2004/08/14 19:37:57 rasky
24 * Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
26 * Revision 1.11 2004/08/05 17:39:56 bernie
29 * Revision 1.10 2004/08/02 20:20:29 aleph
30 * Merge from project_ks
32 * Revision 1.9 2004/07/30 14:24:16 rasky
33 * Task switching con salvataggio perfetto stato di interrupt (SR)
34 * Kernel monitor per dump informazioni su stack dei processi
36 * Revision 1.8 2004/07/30 14:15:53 rasky
37 * Nuovo supporto unificato per detect della CPU
39 * Revision 1.7 2004/07/20 23:26:48 bernie
40 * Fix two errors introduced by previous commit.
42 * Revision 1.6 2004/07/20 23:12:16 bernie
43 * Rationalize and document SCHEDULER_IDLE.
45 * Revision 1.5 2004/07/20 16:20:35 bernie
46 * Move byte-order macros to mware/byteorder.h; Add missing author names.
48 * Revision 1.4 2004/07/20 16:06:04 bernie
49 * Add macros to handle endianess issues.
51 * Revision 1.3 2004/07/18 21:49:51 bernie
54 * Revision 1.2 2004/06/03 11:27:09 bernie
55 * Add dual-license information.
57 * Revision 1.1 2004/05/23 17:48:35 bernie
58 * Add top-level files.
67 // Macros for determining CPU endianness
68 #define CPU_BIG_ENDIAN 0x1234
69 #define CPU_LITTLE_ENDIAN 0x3412
71 // Macros to include cpu-specific version of the headers
72 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
77 #define DISABLE_INTS disable_interrupt()
78 #define ENABLE_INTS enable_interrupt()
79 #define NOP nop_instruction()
81 typedef uint16_t cpuflags_t; // FIXME
82 typedef unsigned int cpustack_t;
84 #define CPU_REG_BITS 16
85 #define CPU_REGS_CNT 16
86 #define CPU_STACK_GROWS_UPWARD 0
87 #define CPU_SP_ON_EMPTY_SLOT 0
88 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
92 #define NOP asm volatile ("nop")
93 #define DISABLE_INTS /* nothing */
94 #define ENABLE_INTS /* nothing */
96 typedef uint32_t cpuflags_t; // FIXME
97 typedef uint32_t cpustack_t;
99 #define CPU_REG_BITS 32
100 #define CPU_REGS_CNT 7
101 #define CPU_STACK_GROWS_UPWARD 0
102 #define CPU_SP_ON_EMPTY_SLOT 0
103 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
108 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
109 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
111 #define DISABLE_IRQSAVE(x) \
112 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
113 #define ENABLE_IRQRESTORE(x) \
114 do { (void)x; asm(move x,SR); } while (0)
116 typedef uint16_t cpuflags_t;
117 typedef unsigned int cpustack_t;
119 #define CPU_REG_BITS 16
120 #define CPU_REGS_CNT FIXME
121 #define CPU_SAVED_REGS_CNT 8
122 #define CPU_STACK_GROWS_UPWARD 1
123 #define CPU_SP_ON_EMPTY_SLOT 0
124 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
126 /* Memory is word-addessed in the DSP56K */
127 #define BITSP_PER_CHAR 16
128 #define SIZEOF_SHORT 1
130 #define SIZEOF_LONG 2
135 #define NOP asm volatile ("nop" ::)
136 #define DISABLE_INTS asm volatile ("cli" ::)
137 #define ENABLE_INTS asm volatile ("sei" ::)
139 #define DISABLE_IRQSAVE(x) \
141 __asm__ __volatile__( \
142 "in %0,__SREG__\n\t" \
144 : "=r" (x) : /* no inputs */ : "cc" \
148 #define ENABLE_IRQRESTORE(x) \
150 __asm__ __volatile__( \
151 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
155 typedef uint8_t cpuflags_t;
156 typedef uint8_t cpustack_t;
158 /* Register counts include SREG too */
159 #define CPU_REG_BITS 8
160 #define CPU_REGS_CNT 33
161 #define CPU_SAVED_REGS_CNT 19
162 #define CPU_STACK_GROWS_UPWARD 0
163 #define CPU_SP_ON_EMPTY_SLOT 1
164 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
167 * Initialization value for registers in stack frame.
168 * The register index is not directly corrispondent to CPU
169 * register numbers. Index 0 is the SREG register: the initial
170 * value is all 0 but the interrupt bit (bit 7).
172 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
177 //! Default for macro not defined in the right arch section
178 #ifndef CPU_REG_INIT_VALUE
179 #define CPU_REG_INIT_VALUE(reg) 0
183 #ifndef CPU_STACK_GROWS_UPWARD
184 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
187 #ifndef CPU_SP_ON_EMPTY_SLOT
188 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
192 * Support stack handling peculiarities of a few CPUs.
194 * Most processors let their stack grow downward and
195 * keep SP pointing at the last pushed value.
197 #if !CPU_STACK_GROWS_UPWARD
198 #if !CPU_SP_ON_EMPTY_SLOT
199 /* Most microprocessors (x86, m68k...) */
200 #define CPU_PUSH_WORD(sp, data) \
201 do { *--(sp) = (data); } while (0)
202 #define CPU_POP_WORD(sp) \
206 #define CPU_PUSH_WORD(sp, data) \
207 do { *(sp)-- = (data); } while (0)
208 #define CPU_POP_WORD(sp) \
212 #else /* CPU_STACK_GROWS_UPWARD */
214 #if !CPU_SP_ON_EMPTY_SLOT
215 /* DSP56K and other weirdos */
216 #define CPU_PUSH_WORD(sp, data) \
217 do { *++(sp) = (cpustack_t)(data); } while (0)
218 #define CPU_POP_WORD(sp) \
221 #error I bet you cannot find a CPU like this
227 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
228 * RTS discards SR while returning (it does not restore it). So we push
229 * 0 to fake the same context.
231 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
233 CPU_PUSH_WORD((sp), (func)); \
234 CPU_PUSH_WORD((sp), 0x100); \
238 /* In AVR, the addresses are pushed into the stack as little-endian, while
239 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
240 * no natural endianess).
242 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
244 uint16_t funcaddr = (uint16_t)(func); \
245 CPU_PUSH_WORD((sp), funcaddr); \
246 CPU_PUSH_WORD((sp), funcaddr>>8); \
250 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
251 CPU_PUSH_WORD((sp), (func))
256 * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
257 * \def BITS_PER_CHAR BITS_PER_SHORT BITS_PER_INT BITS_PER_LONG BITS_PER_PTR
259 * \brief Default type sizes
261 * These defaults are reasonable for most 16/32bit machines.
262 * Some of these macros may be overridden by CPU-specific code above.
264 * ANSI C specifies that the following equations must be true:
266 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
267 * sizeof(float) <= sizeof(double)
269 * BITS_PER_SHORT >= 8
271 * BITS_PER_LONG >= 32
276 #define SIZEOF_CHAR 1
280 #define SIZEOF_SHORT 2
284 #if CPU_REG_BITS < 32
289 #endif /* !SIZEOF_INT */
292 #define SIZEOF_LONG 4
296 #define SIZEOF_PTR SIZEOF_INT
299 #ifndef BITS_PER_CHAR
300 #define BITS_PER_CHAR (SIZEOF_CHAR * 8)
303 #ifndef BITS_PER_SHORT
304 #define BITS_PER_SHORT (SIZEOF_SHORT * BITS_PER_CHAR)
308 #define BITS_PER_INT (SIZEOF_INT * BITS_PER_CHAR)
311 #ifndef BITS_PER_LONG
312 #define BITS_PER_LONG (SIZEOF_LONG * BITS_PER_CHAR)
316 #define BITS_PER_PTR (SIZEOF_PTR * BITS_PER_CHAR)
322 * \def SCHEDULER_IDLE
324 * \brief Invoked by the scheduler to stop the CPU when idle.
326 * This hook can be redefined to put the CPU in low-power mode, or to
327 * profile system load with an external strobe, or to save CPU cycles
328 * in hosted environments such as emulators.
330 #ifndef SCHEDULER_IDLE
331 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
332 /* This emulator hook should yield the CPU to the host. */
334 void SchedulerIdle(void);
336 #define SCHEDULER_IDLE SchedulerIdle()
337 #else /* !ARCH_EMUL */
338 #define SCHEDULER_IDLE do { /* nothing */ } while (0)
339 #endif /* !ARCH_EMUL */
340 #endif /* !SCHEDULER_IDLE */