4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 * Revision 1.6 2004/07/20 23:12:16 bernie
21 * Rationalize and document SCHEDULER_IDLE.
23 * Revision 1.5 2004/07/20 16:20:35 bernie
24 * Move byte-order macros to mware/byteorder.h; Add missing author names.
26 * Revision 1.4 2004/07/20 16:06:04 bernie
27 * Add macros to handle endianess issues.
29 * Revision 1.3 2004/07/18 21:49:51 bernie
32 * Revision 1.2 2004/06/03 11:27:09 bernie
33 * Add dual-license information.
35 * Revision 1.1 2004/05/23 17:48:35 bernie
36 * Add top-level files.
44 //! Initialization value for registers in stack frame
45 #define CPU_REG_INIT_VALUE(reg) 0
47 // Macros for determining CPU endianness
48 #define CPU_BIG_ENDIAN 0x1234
49 #define CPU_LITTLE_ENDIAN 0x3412
52 #if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__) /* 80C196 */
54 #define DISABLE_INTS disable_interrupt()
55 #define ENABLE_INTS enable_interrupt()
56 #define NOP nop_instruction()
58 typedef uint16_t cpuflags_t; // FIXME
59 typedef unsigned int cpustack_t;
61 #define CPU_REGS_CNT 16
62 #define CPU_STACK_GROWS_UPWARD 0
63 #define CPU_SP_ON_EMPTY_SLOT 0
64 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
66 #elif defined(__i386__) || defined(_MSC_VER) /* x86 */
68 #define NOP asm volatile ("nop")
69 #define DISABLE_INTS /* nothing */
70 #define ENABLE_INTS /* nothing */
72 typedef uint32_t cpuflags_t; // FIXME
73 typedef uint32_t cpustack_t;
75 #define CPU_REGS_CNT 7
76 #define CPU_STACK_GROWS_UPWARD 0
77 #define CPU_SP_ON_EMPTY_SLOT 0
78 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
80 #elif defined(__m56800E__) || defined(__m56800__) /* DSP56K */
83 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
84 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
86 #define DISABLE_IRQSAVE(x) \
87 do { asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
88 #define ENABLE_IRQRESTORE(x) \
89 do { asm(move x,SR); } while (0)
91 typedef uint16_t cpuflags_t;
92 typedef unsigned int cpustack_t;
94 #define CPU_REGS_CNT FIXME
95 #define CPU_SAVED_REGS_CNT 28
96 #define CPU_STACK_GROWS_UPWARD 1
97 #define CPU_SP_ON_EMPTY_SLOT 0
98 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
100 #undef CPU_REG_INIT_VALUE
101 INLINE uint16_t CPU_REG_INIT_VALUE(int reg)
106 asm(move OMR, omr_img);
107 return omr_img & (BV(3)/*EX*/ | BV(1)/*MB*/ | BV(0)/*MA*/);
109 else if (reg == 16)/*M01*/
114 #elif defined (__AVR__)
116 #define NOP asm volatile ("nop" ::)
117 #define DISABLE_INTS asm volatile ("cli" ::)
118 #define ENABLE_INTS asm volatile ("sei" ::)
120 #define DISABLE_IRQSAVE(x) \
122 __asm__ __volatile__( \
123 "in %0,__SREG__\n\t" \
125 : "=r" (x) : /* no inputs */ : "cc" \
129 #define ENABLE_IRQRESTORE(x) \
131 __asm__ __volatile__( \
132 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
136 typedef uint8_t cpuflags_t;
137 typedef uint8_t cpustack_t;
139 #define CPU_REGS_CNT 32
140 #define CPU_SAVED_REGS_CNT 18
141 #define CPU_STACK_GROWS_UPWARD 0
142 #define CPU_SP_ON_EMPTY_SLOT 1
143 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
149 #ifndef CPU_STACK_GROWS_UPWARD
150 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
153 #ifndef CPU_SP_ON_EMPTY_SLOT
154 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
158 * Support stack handling peculiarities of a few CPUs.
160 * Most processors let their stack grow downward and
161 * keep SP pointing at the last pushed value.
163 #if !CPU_STACK_GROWS_UPWARD
164 #if !CPU_SP_ON_EMPTY_SLOT
165 /* Most microprocessors (x86, m68k...) */
166 #define CPU_PUSH_WORD(sp, data) \
167 do { *--(sp) = (data); } while (0)
168 #define CPU_POP_WORD(sp) \
172 #define CPU_PUSH_WORD(sp, data) \
173 do { *(sp)-- = (data); } while (0)
174 #define CPU_POP_WORD(sp) \
178 #else /* CPU_STACK_GROWS_UPWARD */
180 #if !CPU_SP_ON_EMPTY_SLOT
181 /* DSP56K and other weirdos */
182 #define CPU_PUSH_WORD(sp, data) \
183 do { *++(sp) = (cpustack_t)(data); } while (0)
184 #define CPU_POP_WORD(sp) \
187 #error I bet you cannot find a CPU like this
192 #if defined(__m56800E__) || defined(__m56800__)
193 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
194 * RTS discards SR while returning (it does not restore it). So we push
195 * 0 to fake the same context.
197 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
199 CPU_PUSH_WORD((sp), (func)); \
200 CPU_PUSH_WORD((sp), 0); \
203 #elif defined (__AVR__)
204 /* In AVR, the addresses are pushed into the stack as little-endian, while
205 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
206 * no natural endianess).
208 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
210 uint16_t funcaddr = (uint16_t)(func); \
211 CPU_PUSH_WORD((sp), funcaddr); \
212 CPU_PUSH_WORD((sp), funcaddr>>8); \
216 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
217 CPU_PUSH_WORD((sp), (func))
222 * \name SCHEDULER_IDLE
224 * \brief Invoked by the scheduler to stop the CPU when idle.
226 * This hook can be redefined to put the CPU in low-power mode, or to
227 * profile system load with an external strobe, or to save CPU cycles
228 * in hosted environments such as emulators.
230 #ifndef SCHEDULER_IDLE
231 #if (ARCH & ARCH_EMUL)
232 /* This emulator hook should yeld the CPU to the host. */
234 void SchedulerIdle(void);
236 #else /* !ARCH_EMUL */
237 #define SCHEDULER_IDLE /* nothing */
238 #endif /* !ARCH_EMUL */
239 #endif /* !SCHEDULER_IDLE */