4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 * Revision 1.11 2004/08/05 17:39:56 bernie
23 * Revision 1.10 2004/08/02 20:20:29 aleph
24 * Merge from project_ks
26 * Revision 1.9 2004/07/30 14:24:16 rasky
27 * Task switching con salvataggio perfetto stato di interrupt (SR)
28 * Kernel monitor per dump informazioni su stack dei processi
30 * Revision 1.8 2004/07/30 14:15:53 rasky
31 * Nuovo supporto unificato per detect della CPU
33 * Revision 1.7 2004/07/20 23:26:48 bernie
34 * Fix two errors introduced by previous commit.
36 * Revision 1.6 2004/07/20 23:12:16 bernie
37 * Rationalize and document SCHEDULER_IDLE.
39 * Revision 1.5 2004/07/20 16:20:35 bernie
40 * Move byte-order macros to mware/byteorder.h; Add missing author names.
42 * Revision 1.4 2004/07/20 16:06:04 bernie
43 * Add macros to handle endianess issues.
45 * Revision 1.3 2004/07/18 21:49:51 bernie
48 * Revision 1.2 2004/06/03 11:27:09 bernie
49 * Add dual-license information.
51 * Revision 1.1 2004/05/23 17:48:35 bernie
52 * Add top-level files.
61 // Macros for determining CPU endianness
62 #define CPU_BIG_ENDIAN 0x1234
63 #define CPU_LITTLE_ENDIAN 0x3412
65 // Macros to include cpu-specific version of the headers
66 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
71 #define DISABLE_INTS disable_interrupt()
72 #define ENABLE_INTS enable_interrupt()
73 #define NOP nop_instruction()
75 typedef uint16_t cpuflags_t; // FIXME
76 typedef unsigned int cpustack_t;
78 #define CPU_REGS_CNT 16
79 #define CPU_STACK_GROWS_UPWARD 0
80 #define CPU_SP_ON_EMPTY_SLOT 0
81 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
85 #define NOP asm volatile ("nop")
86 #define DISABLE_INTS /* nothing */
87 #define ENABLE_INTS /* nothing */
89 typedef uint32_t cpuflags_t; // FIXME
90 typedef uint32_t cpustack_t;
92 #define CPU_REGS_CNT 7
93 #define CPU_STACK_GROWS_UPWARD 0
94 #define CPU_SP_ON_EMPTY_SLOT 0
95 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
100 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
101 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
103 #define DISABLE_IRQSAVE(x) \
104 do { asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
105 #define ENABLE_IRQRESTORE(x) \
106 do { asm(move x,SR); } while (0)
108 typedef uint16_t cpuflags_t;
109 typedef unsigned int cpustack_t;
111 #define CPU_REGS_CNT FIXME
112 #define CPU_SAVED_REGS_CNT 8
113 #define CPU_STACK_GROWS_UPWARD 1
114 #define CPU_SP_ON_EMPTY_SLOT 0
115 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
119 #define NOP asm volatile ("nop" ::)
120 #define DISABLE_INTS asm volatile ("cli" ::)
121 #define ENABLE_INTS asm volatile ("sei" ::)
123 #define DISABLE_IRQSAVE(x) \
125 __asm__ __volatile__( \
126 "in %0,__SREG__\n\t" \
128 : "=r" (x) : /* no inputs */ : "cc" \
132 #define ENABLE_IRQRESTORE(x) \
134 __asm__ __volatile__( \
135 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
139 typedef uint8_t cpuflags_t;
140 typedef uint8_t cpustack_t;
142 /* Register counts include SREG too */
143 #define CPU_REGS_CNT 33
144 #define CPU_SAVED_REGS_CNT 19
145 #define CPU_STACK_GROWS_UPWARD 0
146 #define CPU_SP_ON_EMPTY_SLOT 1
147 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
150 * Initialization value for registers in stack frame.
151 * The register index is not directly corrispondent to CPU
152 * register numbers. Index 0 is the SREG register: the initial
153 * value is all 0 but the interrupt bit (bit 7).
155 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
160 //! Default for macro not defined in the right arch section
161 #ifndef CPU_REG_INIT_VALUE
162 #define CPU_REG_INIT_VALUE(reg) 0
166 #ifndef CPU_STACK_GROWS_UPWARD
167 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
170 #ifndef CPU_SP_ON_EMPTY_SLOT
171 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
175 * Support stack handling peculiarities of a few CPUs.
177 * Most processors let their stack grow downward and
178 * keep SP pointing at the last pushed value.
180 #if !CPU_STACK_GROWS_UPWARD
181 #if !CPU_SP_ON_EMPTY_SLOT
182 /* Most microprocessors (x86, m68k...) */
183 #define CPU_PUSH_WORD(sp, data) \
184 do { *--(sp) = (data); } while (0)
185 #define CPU_POP_WORD(sp) \
189 #define CPU_PUSH_WORD(sp, data) \
190 do { *(sp)-- = (data); } while (0)
191 #define CPU_POP_WORD(sp) \
195 #else /* CPU_STACK_GROWS_UPWARD */
197 #if !CPU_SP_ON_EMPTY_SLOT
198 /* DSP56K and other weirdos */
199 #define CPU_PUSH_WORD(sp, data) \
200 do { *++(sp) = (cpustack_t)(data); } while (0)
201 #define CPU_POP_WORD(sp) \
204 #error I bet you cannot find a CPU like this
210 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
211 * RTS discards SR while returning (it does not restore it). So we push
212 * 0 to fake the same context.
214 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
216 CPU_PUSH_WORD((sp), (func)); \
217 CPU_PUSH_WORD((sp), 0x100); \
221 /* In AVR, the addresses are pushed into the stack as little-endian, while
222 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
223 * no natural endianess).
225 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
227 uint16_t funcaddr = (uint16_t)(func); \
228 CPU_PUSH_WORD((sp), funcaddr); \
229 CPU_PUSH_WORD((sp), funcaddr>>8); \
233 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
234 CPU_PUSH_WORD((sp), (func))
239 * \def SCHEDULER_IDLE
241 * \brief Invoked by the scheduler to stop the CPU when idle.
243 * This hook can be redefined to put the CPU in low-power mode, or to
244 * profile system load with an external strobe, or to save CPU cycles
245 * in hosted environments such as emulators.
247 #ifndef SCHEDULER_IDLE
248 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
249 /* This emulator hook should yeld the CPU to the host. */
251 void SchedulerIdle(void);
253 #else /* !ARCH_EMUL */
254 #define SCHEDULER_IDLE /* nothing */
255 #endif /* !ARCH_EMUL */
256 #endif /* !SCHEDULER_IDLE */