4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.29 2005/02/16 20:33:24 bernie
21 *#* Preliminary PPC support.
23 *#* Revision 1.28 2004/12/31 17:39:41 bernie
24 *#* Fix documentation.
26 *#* Revision 1.27 2004/12/31 17:02:47 bernie
27 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
29 *#* Revision 1.26 2004/12/13 12:08:12 bernie
30 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
32 *#* Revision 1.25 2004/12/08 08:31:02 bernie
33 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
38 #include "compiler.h" /* for uintXX_t */
42 * \name Macros for determining CPU endianness.
45 #define CPU_BIG_ENDIAN 0x1234
46 #define CPU_LITTLE_ENDIAN 0x3412
49 /*! Macro to include cpu-specific versions of the headers. */
50 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
55 #define NOP nop_instruction()
56 #define IRQ_DISABLE disable_interrupt()
57 #define IRQ_ENABLE enable_interrupt()
59 typedef uint16_t cpuflags_t; // FIXME
60 typedef unsigned int cpustack_t;
62 #define CPU_REG_BITS 16
63 #define CPU_REGS_CNT 16
64 #define CPU_STACK_GROWS_UPWARD 0
65 #define CPU_SP_ON_EMPTY_SLOT 0
66 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
71 #define NOP asm volatile ("nop")
72 #define IRQ_DISABLE /* nothing */
73 #define IRQ_ENABLE /* nothing */
74 #define IRQ_SAVE_DISABLE(x) /* nothing */
75 #define IRQ_RESTORE(x) /* nothing */
77 typedef uint32_t cpuflags_t; // FIXME
78 typedef uint32_t cpustack_t;
80 #define CPU_REG_BITS 32
81 #define CPU_REGS_CNT 7
82 #define CPU_STACK_GROWS_UPWARD 0
83 #define CPU_SP_ON_EMPTY_SLOT 0
84 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
88 #define NOP asm volatile ("nop" ::)
89 #define IRQ_DISABLE FIXME
90 #define IRQ_ENABLE FIXME
91 #define IRQ_SAVE_DISABLE(x) FIXME
92 #define IRQ_RESTORE(x) FIXME
93 #define IRQ_GETSTATE() FIXME
95 typedef uint32_t cpuflags_t; // FIXME
96 typedef uint32_t cpustack_t; // FIXME
98 /* Register counts include SREG too */
99 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
100 #define CPU_REGS_CNT FIXME
101 #define CPU_SAVED_REGS_CNT FIXME
102 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
103 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
104 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
105 #define CPU_HARVARD 0
110 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
111 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
113 #define IRQ_SAVE_DISABLE(x) \
114 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
115 #define IRQ_RESTORE(x) \
116 do { (void)x; asm(move x,SR); } while (0)
119 typedef uint16_t cpuflags_t;
120 typedef unsigned int cpustack_t;
122 #define CPU_REG_BITS 16
123 #define CPU_REGS_CNT FIXME
124 #define CPU_SAVED_REGS_CNT 8
125 #define CPU_STACK_GROWS_UPWARD 1
126 #define CPU_SP_ON_EMPTY_SLOT 0
127 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
128 #define CPU_HARVARD 1
130 /* Memory is word-addessed in the DSP56K */
131 #define CPU_BITS_PER_CHAR 16
132 #define SIZEOF_SHORT 1
134 #define SIZEOF_LONG 2
139 #define NOP asm volatile ("nop" ::)
140 #define IRQ_DISABLE asm volatile ("cli" ::)
141 #define IRQ_ENABLE asm volatile ("sei" ::)
143 #define IRQ_SAVE_DISABLE(x) \
145 __asm__ __volatile__( \
146 "in %0,__SREG__\n\t" \
148 : "=r" (x) : /* no inputs */ : "cc" \
152 #define IRQ_RESTORE(x) \
154 __asm__ __volatile__( \
155 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
159 #define IRQ_GETSTATE() \
162 __asm__ __volatile__( \
163 "in %0,__SREG__\n\t" \
164 : "=r" (sreg) /* no inputs & no clobbers */ \
166 (bool)(sreg & 0x80); \
169 typedef uint8_t cpuflags_t;
170 typedef uint8_t cpustack_t;
172 /* Register counts include SREG too */
173 #define CPU_REG_BITS 8
174 #define CPU_REGS_CNT 33
175 #define CPU_SAVED_REGS_CNT 19
176 #define CPU_STACK_GROWS_UPWARD 0
177 #define CPU_SP_ON_EMPTY_SLOT 1
178 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
179 #define CPU_HARVARD 1
182 * Initialization value for registers in stack frame.
183 * The register index is not directly corrispondent to CPU
184 * register numbers. Index 0 is the SREG register: the initial
185 * value is all 0 but the interrupt bit (bit 7).
187 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
192 * Execute \a CODE atomically with respect to interrupts.
194 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
196 #define ATOMIC(CODE) \
198 cpuflags_t __flags; \
199 IRQ_SAVE_DISABLE(__flags); \
201 IRQ_RESTORE(__flags); \
205 //! Default for macro not defined in the right arch section
206 #ifndef CPU_REG_INIT_VALUE
207 #define CPU_REG_INIT_VALUE(reg) 0
211 #ifndef CPU_STACK_GROWS_UPWARD
212 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
215 #ifndef CPU_SP_ON_EMPTY_SLOT
216 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
220 * Support stack handling peculiarities of a few CPUs.
222 * Most processors let their stack grow downward and
223 * keep SP pointing at the last pushed value.
225 #if !CPU_STACK_GROWS_UPWARD
226 #if !CPU_SP_ON_EMPTY_SLOT
227 /* Most microprocessors (x86, m68k...) */
228 #define CPU_PUSH_WORD(sp, data) \
229 do { *--(sp) = (data); } while (0)
230 #define CPU_POP_WORD(sp) \
234 #define CPU_PUSH_WORD(sp, data) \
235 do { *(sp)-- = (data); } while (0)
236 #define CPU_POP_WORD(sp) \
240 #else /* CPU_STACK_GROWS_UPWARD */
242 #if !CPU_SP_ON_EMPTY_SLOT
243 /* DSP56K and other weirdos */
244 #define CPU_PUSH_WORD(sp, data) \
245 do { *++(sp) = (cpustack_t)(data); } while (0)
246 #define CPU_POP_WORD(sp) \
249 #error I bet you cannot find a CPU like this
256 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
257 * RTS discards SR while returning (it does not restore it). So we push
258 * 0 to fake the same context.
260 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
262 CPU_PUSH_WORD((sp), (func)); \
263 CPU_PUSH_WORD((sp), 0x100); \
268 * In AVR, the addresses are pushed into the stack as little-endian, while
269 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
270 * no natural endianess).
272 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
274 uint16_t funcaddr = (uint16_t)(func); \
275 CPU_PUSH_WORD((sp), funcaddr); \
276 CPU_PUSH_WORD((sp), funcaddr>>8); \
280 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
281 CPU_PUSH_WORD((sp), (func))
286 * \name Default type sizes.
288 * These defaults are reasonable for most 16/32bit machines.
289 * Some of these macros may be overridden by CPU-specific code above.
291 * ANSI C requires that the following equations be true:
293 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
294 * sizeof(float) <= sizeof(double)
295 * CPU_BITS_PER_CHAR >= 8
296 * CPU_BITS_PER_SHORT >= 8
297 * CPU_BITS_PER_INT >= 16
298 * CPU_BITS_PER_LONG >= 32
303 #define SIZEOF_CHAR 1
307 #define SIZEOF_SHORT 2
311 #if CPU_REG_BITS < 32
316 #endif /* !SIZEOF_INT */
319 #if CPU_REG_BITS > 32
320 #define SIZEOF_LONG 8
322 #define SIZEOF_LONG 4
327 #define SIZEOF_PTR SIZEOF_INT
330 #ifndef CPU_BITS_PER_CHAR
331 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
334 #ifndef CPU_BITS_PER_SHORT
335 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
338 #ifndef CPU_BITS_PER_INT
339 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
342 #ifndef CPU_BITS_PER_LONG
343 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
346 #ifndef CPU_BITS_PER_PTR
347 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
351 /* Sanity checks for the above definitions */
352 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
353 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
354 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
355 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
361 * \brief Invoked by the scheduler to stop the CPU when idle.
363 * This hook can be redefined to put the CPU in low-power mode, or to
364 * profile system load with an external strobe, or to save CPU cycles
365 * in hosted environments such as emulators.
368 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
369 /* This emulator hook should yield the CPU to the host. */
371 void SchedulerIdle(void);
373 #define CPU_IDLE SchedulerIdle()
374 #else /* !ARCH_EMUL */
375 #define CPU_IDLE do { /* nothing */ } while (0)
376 #endif /* !ARCH_EMUL */
377 #endif /* !CPU_IDLE */
380 #define SCHEDULER_IDLE CPU_IDLE
382 #endif /* DEVLIB_CPU_H */