4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.6 2005/07/19 07:26:49 bernie
21 *#* Add missing #endif.
23 *#* Revision 1.5 2005/06/27 21:24:17 bernie
24 *#* CPU_CSOURCE(): New macro.
26 *#* Revision 1.4 2005/06/14 06:15:10 bernie
27 *#* Add X86_64 support.
29 *#* Revision 1.3 2005/04/12 04:06:17 bernie
30 *#* Catch missing CPU earlier.
32 *#* Revision 1.2 2005/04/11 19:10:27 bernie
33 *#* Include top-level headers from cfg/ subdir.
35 *#* Revision 1.1 2005/04/11 19:04:13 bernie
36 *#* Move top-level headers to cfg/ subdir.
38 *#* Revision 1.30 2005/03/15 00:20:09 bernie
39 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
41 *#* Revision 1.29 2005/02/16 20:33:24 bernie
42 *#* Preliminary PPC support.
44 *#* Revision 1.28 2004/12/31 17:39:41 bernie
45 *#* Fix documentation.
47 *#* Revision 1.27 2004/12/31 17:02:47 bernie
48 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
50 *#* Revision 1.26 2004/12/13 12:08:12 bernie
51 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
53 *#* Revision 1.25 2004/12/08 08:31:02 bernie
54 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
59 #include <cfg/compiler.h> /* for uintXX_t */
63 * \name Macros for determining CPU endianness.
66 #define CPU_BIG_ENDIAN 0x1234
67 #define CPU_LITTLE_ENDIAN 0x3412
70 /*! Macro to include cpu-specific versions of the headers. */
71 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
73 /*! Macro to include cpu-specific versions of implementation files. */
74 #define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
79 #define NOP nop_instruction()
80 #define IRQ_DISABLE disable_interrupt()
81 #define IRQ_ENABLE enable_interrupt()
83 typedef uint16_t cpuflags_t; // FIXME
84 typedef unsigned int cpustack_t;
86 #define CPU_REG_BITS 16
87 #define CPU_REGS_CNT 16
88 #define CPU_STACK_GROWS_UPWARD 0
89 #define CPU_SP_ON_EMPTY_SLOT 0
90 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
95 #define NOP asm volatile ("nop")
96 #define IRQ_DISABLE FIXME
97 #define IRQ_ENABLE FIXME
98 #define IRQ_SAVE_DISABLE(x) FIXME
99 #define IRQ_RESTORE(x) FIXME
101 typedef uint32_t cpuflags_t; // FIXME
103 #define CPU_REGS_CNT 7
104 #define CPU_STACK_GROWS_UPWARD 0
105 #define CPU_SP_ON_EMPTY_SLOT 0
106 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
107 #define CPU_HARVARD 0
110 typedef uint64_t cpustack_t;
111 #define CPU_REG_BITS 64
114 /* WIN64 is an IL32-P64 weirdo. */
115 #define SIZEOF_LONG 4
118 typedef uint32_t cpustack_t;
119 #define CPU_REG_BITS 32
123 #define NOP asm volatile ("nop" ::)
124 #define IRQ_DISABLE FIXME
125 #define IRQ_ENABLE FIXME
126 #define IRQ_SAVE_DISABLE(x) FIXME
127 #define IRQ_RESTORE(x) FIXME
128 #define IRQ_GETSTATE() FIXME
130 typedef uint32_t cpuflags_t; // FIXME
131 typedef uint32_t cpustack_t; // FIXME
133 /* Register counts include SREG too */
134 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
135 #define CPU_REGS_CNT FIXME
136 #define CPU_SAVED_REGS_CNT FIXME
137 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
138 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
139 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
140 #define CPU_HARVARD 0
145 #define BREAKPOINT asm(debug)
146 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
147 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
149 #define IRQ_SAVE_DISABLE(x) \
150 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
151 #define IRQ_RESTORE(x) \
152 do { (void)x; asm(move x,SR); } while (0)
154 static inline bool irq_running(void)
156 extern void *user_sp;
159 #define IRQ_RUNNING() irq_running()
161 static inline bool irq_getstate(void)
165 return !(x & 0x0200);
167 #define IRQ_GETSTATE() irq_getstate()
169 typedef uint16_t cpuflags_t;
170 typedef unsigned int cpustack_t;
172 #define CPU_REG_BITS 16
173 #define CPU_REGS_CNT FIXME
174 #define CPU_SAVED_REGS_CNT 8
175 #define CPU_STACK_GROWS_UPWARD 1
176 #define CPU_SP_ON_EMPTY_SLOT 0
177 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
178 #define CPU_HARVARD 1
180 /* Memory is word-addessed in the DSP56K */
181 #define CPU_BITS_PER_CHAR 16
182 #define SIZEOF_SHORT 1
184 #define SIZEOF_LONG 2
189 #define NOP asm volatile ("nop" ::)
190 #define IRQ_DISABLE asm volatile ("cli" ::)
191 #define IRQ_ENABLE asm volatile ("sei" ::)
193 #define IRQ_SAVE_DISABLE(x) \
195 __asm__ __volatile__( \
196 "in %0,__SREG__\n\t" \
198 : "=r" (x) : /* no inputs */ : "cc" \
202 #define IRQ_RESTORE(x) \
204 __asm__ __volatile__( \
205 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
209 #define IRQ_GETSTATE() \
212 __asm__ __volatile__( \
213 "in %0,__SREG__\n\t" \
214 : "=r" (sreg) /* no inputs & no clobbers */ \
216 (bool)(sreg & 0x80); \
219 typedef uint8_t cpuflags_t;
220 typedef uint8_t cpustack_t;
222 /* Register counts include SREG too */
223 #define CPU_REG_BITS 8
224 #define CPU_REGS_CNT 33
225 #define CPU_SAVED_REGS_CNT 19
226 #define CPU_STACK_GROWS_UPWARD 0
227 #define CPU_SP_ON_EMPTY_SLOT 1
228 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
229 #define CPU_HARVARD 1
232 * Initialization value for registers in stack frame.
233 * The register index is not directly corrispondent to CPU
234 * register numbers. Index 0 is the SREG register: the initial
235 * value is all 0 but the interrupt bit (bit 7).
237 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
240 #error No CPU_... defined.
244 * Execute \a CODE atomically with respect to interrupts.
246 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
248 #define ATOMIC(CODE) \
250 cpuflags_t __flags; \
251 IRQ_SAVE_DISABLE(__flags); \
253 IRQ_RESTORE(__flags); \
257 //! Default for macro not defined in the right arch section
258 #ifndef CPU_REG_INIT_VALUE
259 #define CPU_REG_INIT_VALUE(reg) 0
263 #ifndef CPU_STACK_GROWS_UPWARD
264 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
267 #ifndef CPU_SP_ON_EMPTY_SLOT
268 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
272 * Support stack handling peculiarities of a few CPUs.
274 * Most processors let their stack grow downward and
275 * keep SP pointing at the last pushed value.
277 #if !CPU_STACK_GROWS_UPWARD
278 #if !CPU_SP_ON_EMPTY_SLOT
279 /* Most microprocessors (x86, m68k...) */
280 #define CPU_PUSH_WORD(sp, data) \
281 do { *--(sp) = (data); } while (0)
282 #define CPU_POP_WORD(sp) \
286 #define CPU_PUSH_WORD(sp, data) \
287 do { *(sp)-- = (data); } while (0)
288 #define CPU_POP_WORD(sp) \
292 #else /* CPU_STACK_GROWS_UPWARD */
294 #if !CPU_SP_ON_EMPTY_SLOT
295 /* DSP56K and other weirdos */
296 #define CPU_PUSH_WORD(sp, data) \
297 do { *++(sp) = (cpustack_t)(data); } while (0)
298 #define CPU_POP_WORD(sp) \
301 #error I bet you cannot find a CPU like this
308 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
309 * RTS discards SR while returning (it does not restore it). So we push
310 * 0 to fake the same context.
312 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
314 CPU_PUSH_WORD((sp), (func)); \
315 CPU_PUSH_WORD((sp), 0x100); \
320 * In AVR, the addresses are pushed into the stack as little-endian, while
321 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
322 * no natural endianess).
324 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
326 uint16_t funcaddr = (uint16_t)(func); \
327 CPU_PUSH_WORD((sp), funcaddr); \
328 CPU_PUSH_WORD((sp), funcaddr>>8); \
332 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
333 CPU_PUSH_WORD((sp), (func))
338 * \name Default type sizes.
340 * These defaults are reasonable for most 16/32bit machines.
341 * Some of these macros may be overridden by CPU-specific code above.
343 * ANSI C requires that the following equations be true:
345 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
346 * sizeof(float) <= sizeof(double)
347 * CPU_BITS_PER_CHAR >= 8
348 * CPU_BITS_PER_SHORT >= 8
349 * CPU_BITS_PER_INT >= 16
350 * CPU_BITS_PER_LONG >= 32
355 #define SIZEOF_CHAR 1
359 #define SIZEOF_SHORT 2
363 #if CPU_REG_BITS < 32
368 #endif /* !SIZEOF_INT */
371 #if CPU_REG_BITS > 32
372 #define SIZEOF_LONG 8
374 #define SIZEOF_LONG 4
379 #if CPU_REG_BITS < 32
381 #elif CPU_REG_BITS == 32
383 #else /* CPU_REG_BITS > 32 */
388 #ifndef CPU_BITS_PER_CHAR
389 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
392 #ifndef CPU_BITS_PER_SHORT
393 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
396 #ifndef CPU_BITS_PER_INT
397 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
400 #ifndef CPU_BITS_PER_LONG
401 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
404 #ifndef CPU_BITS_PER_PTR
405 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
409 #define BREAKPOINT /* nop */
414 /* Sanity checks for the above definitions */
415 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
416 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
417 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
418 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
419 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
420 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
421 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
422 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
423 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
424 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
425 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
426 #ifdef __HAS_INT64_T__
427 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
428 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
434 * \brief Invoked by the scheduler to stop the CPU when idle.
436 * This hook can be redefined to put the CPU in low-power mode, or to
437 * profile system load with an external strobe, or to save CPU cycles
438 * in hosted environments such as emulators.
441 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
442 /* This emulator hook should yield the CPU to the host. */
444 void SchedulerIdle(void);
446 #define CPU_IDLE SchedulerIdle()
447 #else /* !ARCH_EMUL */
448 #define CPU_IDLE do { /* nothing */ } while (0)
449 #endif /* !ARCH_EMUL */
450 #endif /* !CPU_IDLE */
453 #define SCHEDULER_IDLE CPU_IDLE
455 #endif /* DEVLIB_CPU_H */