4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.25 2004/12/08 08:31:02 bernie
21 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
23 *#* Revision 1.24 2004/12/08 08:04:13 bernie
26 *#* Revision 1.23 2004/11/16 22:41:58 bernie
27 *#* Support 64bit CPUs.
29 *#* Revision 1.22 2004/11/16 21:57:59 bernie
30 *#* CPU_IDLE: Rename from SCHEDULER_IDLE.
32 *#* Revision 1.21 2004/11/16 21:34:25 bernie
33 *#* Commonize obsolete names for IRQ macros; Doxygen fixes.
35 *#* Revision 1.20 2004/11/16 20:33:32 bernie
36 *#* CPU_HARVARD: New macro.
38 *#* Revision 1.19 2004/10/03 20:43:54 bernie
39 *#* Fix Doxygen markup.
41 *#* Revision 1.18 2004/10/03 18:36:31 bernie
42 *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
44 *#* Revision 1.17 2004/09/06 21:48:27 bernie
45 *#* ATOMIC(): New macro.
47 *#* Revision 1.16 2004/08/29 21:58:33 bernie
48 *#* Rename BITS_PER_XYZ macros; Add sanity checks.
50 *#* Revision 1.15 2004/08/25 14:12:08 rasky
51 *#* Aggiornato il comment block dei log RCS
53 *#* Revision 1.14 2004/08/24 13:29:28 bernie
54 *#* Trim CVS log; Rename header guards.
56 *#* Revision 1.12 2004/08/14 19:37:57 rasky
57 *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
59 *#* Revision 1.11 2004/08/05 17:39:56 bernie
60 *#* Fix a Doxygen tag.
62 *#* Revision 1.10 2004/08/02 20:20:29 aleph
63 *#* Merge from project_ks
65 *#* Revision 1.9 2004/07/30 14:24:16 rasky
66 *#* Task switching con salvataggio perfetto stato di interrupt (SR)
67 *#* Kernel monitor per dump informazioni su stack dei processi
72 #include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
76 * \name Macros for determining CPU endianness.
79 #define CPU_BIG_ENDIAN 0x1234
80 #define CPU_LITTLE_ENDIAN 0x3412
83 /*! Macro to include cpu-specific versions of the headers. */
84 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
89 #define NOP nop_instruction()
90 #define IRQ_DISABLE disable_interrupt()
91 #define IRQ_ENABLE enable_interrupt()
93 typedef uint16_t cpuflags_t; // FIXME
94 typedef unsigned int cpustack_t;
96 #define CPU_REG_BITS 16
97 #define CPU_REGS_CNT 16
98 #define CPU_STACK_GROWS_UPWARD 0
99 #define CPU_SP_ON_EMPTY_SLOT 0
100 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
101 #define CPU_HARVARD 0
105 #define NOP asm volatile ("nop")
106 #define IRQ_DISABLE /* nothing */
107 #define IRQ_ENABLE /* nothing */
109 typedef uint32_t cpuflags_t; // FIXME
110 typedef uint32_t cpustack_t;
112 #define CPU_REG_BITS 32
113 #define CPU_REGS_CNT 7
114 #define CPU_STACK_GROWS_UPWARD 0
115 #define CPU_SP_ON_EMPTY_SLOT 0
116 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
117 #define CPU_HARVARD 0
122 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
123 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
125 #define IRQ_SAVE_DISABLE(x) \
126 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
127 #define IRQ_RESTORE(x) \
128 do { (void)x; asm(move x,SR); } while (0)
131 typedef uint16_t cpuflags_t;
132 typedef unsigned int cpustack_t;
134 #define CPU_REG_BITS 16
135 #define CPU_REGS_CNT FIXME
136 #define CPU_SAVED_REGS_CNT 8
137 #define CPU_STACK_GROWS_UPWARD 1
138 #define CPU_SP_ON_EMPTY_SLOT 0
139 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
140 #define CPU_HARVARD 1
142 /* Memory is word-addessed in the DSP56K */
143 #define CPU_BITS_PER_CHAR 16
144 #define SIZEOF_SHORT 1
146 #define SIZEOF_LONG 2
151 #define NOP asm volatile ("nop" ::)
152 #define IRQ_DISABLE asm volatile ("cli" ::)
153 #define IRQ_ENABLE asm volatile ("sei" ::)
155 #define IRQ_SAVE_DISABLE(x) \
157 __asm__ __volatile__( \
158 "in %0,__SREG__\n\t" \
160 : "=r" (x) : /* no inputs */ : "cc" \
164 #define IRQ_RESTORE(x) \
166 __asm__ __volatile__( \
167 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
171 #define IRQ_GETSTATE() \
174 __asm__ __volatile__( \
175 "in %0,__SREG__\n\t" \
176 : "=r" (sreg) /* no inputs & no clobbers */ \
178 (bool)(sreg & 0x80); \
181 typedef uint8_t cpuflags_t;
182 typedef uint8_t cpustack_t;
184 /* Register counts include SREG too */
185 #define CPU_REG_BITS 8
186 #define CPU_REGS_CNT 33
187 #define CPU_SAVED_REGS_CNT 19
188 #define CPU_STACK_GROWS_UPWARD 0
189 #define CPU_SP_ON_EMPTY_SLOT 1
190 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
191 #define CPU_HARVARD 1
194 * Initialization value for registers in stack frame.
195 * The register index is not directly corrispondent to CPU
196 * register numbers. Index 0 is the SREG register: the initial
197 * value is all 0 but the interrupt bit (bit 7).
199 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
204 #define DISABLE_INTS IRQ_DISABLE
205 #define ENABLE_INTS IRQ_ENABLE
206 #define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x)
207 #define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
210 * Execute \a CODE atomically with respect to interrupts.
212 * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
214 #define ATOMIC(CODE) \
216 cpuflags_t __flags; \
217 DISABLE_IRQSAVE(__flags); \
219 ENABLE_IRQRESTORE(__flags); \
223 //! Default for macro not defined in the right arch section
224 #ifndef CPU_REG_INIT_VALUE
225 #define CPU_REG_INIT_VALUE(reg) 0
229 #ifndef CPU_STACK_GROWS_UPWARD
230 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
233 #ifndef CPU_SP_ON_EMPTY_SLOT
234 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
238 * Support stack handling peculiarities of a few CPUs.
240 * Most processors let their stack grow downward and
241 * keep SP pointing at the last pushed value.
243 #if !CPU_STACK_GROWS_UPWARD
244 #if !CPU_SP_ON_EMPTY_SLOT
245 /* Most microprocessors (x86, m68k...) */
246 #define CPU_PUSH_WORD(sp, data) \
247 do { *--(sp) = (data); } while (0)
248 #define CPU_POP_WORD(sp) \
252 #define CPU_PUSH_WORD(sp, data) \
253 do { *(sp)-- = (data); } while (0)
254 #define CPU_POP_WORD(sp) \
258 #else /* CPU_STACK_GROWS_UPWARD */
260 #if !CPU_SP_ON_EMPTY_SLOT
261 /* DSP56K and other weirdos */
262 #define CPU_PUSH_WORD(sp, data) \
263 do { *++(sp) = (cpustack_t)(data); } while (0)
264 #define CPU_POP_WORD(sp) \
267 #error I bet you cannot find a CPU like this
274 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
275 * RTS discards SR while returning (it does not restore it). So we push
276 * 0 to fake the same context.
278 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
280 CPU_PUSH_WORD((sp), (func)); \
281 CPU_PUSH_WORD((sp), 0x100); \
286 * In AVR, the addresses are pushed into the stack as little-endian, while
287 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
288 * no natural endianess).
290 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
292 uint16_t funcaddr = (uint16_t)(func); \
293 CPU_PUSH_WORD((sp), funcaddr); \
294 CPU_PUSH_WORD((sp), funcaddr>>8); \
298 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
299 CPU_PUSH_WORD((sp), (func))
304 * \name Default type sizes.
306 * These defaults are reasonable for most 16/32bit machines.
307 * Some of these macros may be overridden by CPU-specific code above.
309 * ANSI C requires that the following equations be true:
311 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
312 * sizeof(float) <= sizeof(double)
313 * CPU_BITS_PER_CHAR >= 8
314 * CPU_BITS_PER_SHORT >= 8
315 * CPU_BITS_PER_INT >= 16
316 * CPU_BITS_PER_LONG >= 32
321 #define SIZEOF_CHAR 1
325 #define SIZEOF_SHORT 2
329 #if CPU_REG_BITS < 32
334 #endif /* !SIZEOF_INT */
337 #if CPU_REG_BITS > 32
338 #define SIZEOF_LONG 8
340 #define SIZEOF_LONG 4
345 #define SIZEOF_PTR SIZEOF_INT
348 #ifndef CPU_BITS_PER_CHAR
349 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
352 #ifndef CPU_BITS_PER_SHORT
353 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
356 #ifndef CPU_BITS_PER_INT
357 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
360 #ifndef CPU_BITS_PER_LONG
361 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
364 #ifndef CPU_BITS_PER_PTR
365 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
369 /* Sanity checks for the above definitions */
370 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
371 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
372 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
373 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
377 * \def SCHEDULER_IDLE
379 * \brief Invoked by the scheduler to stop the CPU when idle.
381 * This hook can be redefined to put the CPU in low-power mode, or to
382 * profile system load with an external strobe, or to save CPU cycles
383 * in hosted environments such as emulators.
386 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
387 /* This emulator hook should yield the CPU to the host. */
389 void SchedulerIdle(void);
391 #define CPU_IDLE SchedulerIdle()
392 #else /* !ARCH_EMUL */
393 #define CPU_IDLE do { /* nothing */ } while (0)
394 #endif /* !ARCH_EMUL */
395 #endif /* !CPU_IDLE */
398 #define SCHEDULER_IDLE CPU_IDLE
400 #endif /* DEVLIB_CPU_H */