4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.18 2004/10/03 18:36:31 bernie
21 *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
23 *#* Revision 1.17 2004/09/06 21:48:27 bernie
24 *#* ATOMIC(): New macro.
26 *#* Revision 1.16 2004/08/29 21:58:33 bernie
27 *#* Rename BITS_PER_XYZ macros; Add sanity checks.
29 *#* Revision 1.15 2004/08/25 14:12:08 rasky
30 *#* Aggiornato il comment block dei log RCS
32 *#* Revision 1.14 2004/08/24 13:29:28 bernie
33 *#* Trim CVS log; Rename header guards.
35 *#* Revision 1.12 2004/08/14 19:37:57 rasky
36 *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
38 *#* Revision 1.11 2004/08/05 17:39:56 bernie
39 *#* Fix a Doxygen tag.
41 *#* Revision 1.10 2004/08/02 20:20:29 aleph
42 *#* Merge from project_ks
44 *#* Revision 1.9 2004/07/30 14:24:16 rasky
45 *#* Task switching con salvataggio perfetto stato di interrupt (SR)
46 *#* Kernel monitor per dump informazioni su stack dei processi
51 #include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
54 // Macros for determining CPU endianness
55 #define CPU_BIG_ENDIAN 0x1234
56 #define CPU_LITTLE_ENDIAN 0x3412
58 // Macros to include cpu-specific version of the headers
59 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
64 #define DISABLE_INTS disable_interrupt()
65 #define ENABLE_INTS enable_interrupt()
66 #define NOP nop_instruction()
68 typedef uint16_t cpuflags_t; // FIXME
69 typedef unsigned int cpustack_t;
71 #define CPU_REG_BITS 16
72 #define CPU_REGS_CNT 16
73 #define CPU_STACK_GROWS_UPWARD 0
74 #define CPU_SP_ON_EMPTY_SLOT 0
75 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
79 #define NOP asm volatile ("nop")
80 #define DISABLE_INTS /* nothing */
81 #define ENABLE_INTS /* nothing */
83 typedef uint32_t cpuflags_t; // FIXME
84 typedef uint32_t cpustack_t;
86 #define CPU_REG_BITS 32
87 #define CPU_REGS_CNT 7
88 #define CPU_STACK_GROWS_UPWARD 0
89 #define CPU_SP_ON_EMPTY_SLOT 0
90 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
95 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
96 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
98 #define DISABLE_IRQSAVE(x) \
99 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
100 #define ENABLE_IRQRESTORE(x) \
101 do { (void)x; asm(move x,SR); } while (0)
103 typedef uint16_t cpuflags_t;
104 typedef unsigned int cpustack_t;
106 #define CPU_REG_BITS 16
107 #define CPU_REGS_CNT FIXME
108 #define CPU_SAVED_REGS_CNT 8
109 #define CPU_STACK_GROWS_UPWARD 1
110 #define CPU_SP_ON_EMPTY_SLOT 0
111 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
113 /* Memory is word-addessed in the DSP56K */
114 #define CPU_BITS_PER_CHAR 16
115 #define SIZEOF_SHORT 1
117 #define SIZEOF_LONG 2
122 #define NOP asm volatile ("nop" ::)
123 #define IRQ_DISABLE asm volatile ("cli" ::)
124 #define IRQ_ENABLE asm volatile ("sei" ::)
126 #define IRQ_SAVE_DISABLE(x) \
128 __asm__ __volatile__( \
129 "in %0,__SREG__\n\t" \
131 : "=r" (x) : /* no inputs */ : "cc" \
135 #define IRQ_RESTORE(x) \
137 __asm__ __volatile__( \
138 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
142 #define IRQ_GETSTATE() \
145 __asm__ __volatile__( \
146 "in %0,__SREG__\n\t" \
147 : "=r" (sreg) /* no inputs & no clobbers */ \
149 (bool)(sreg & 0x80); \
153 #define DISABLE_INTS IRQ_DISABLE
154 #define ENABLE_INTS IRQ_ENABLE
155 #define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x)
156 #define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
158 typedef uint8_t cpuflags_t;
159 typedef uint8_t cpustack_t;
161 /* Register counts include SREG too */
162 #define CPU_REG_BITS 8
163 #define CPU_REGS_CNT 33
164 #define CPU_SAVED_REGS_CNT 19
165 #define CPU_STACK_GROWS_UPWARD 0
166 #define CPU_SP_ON_EMPTY_SLOT 1
167 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
170 * Initialization value for registers in stack frame.
171 * The register index is not directly corrispondent to CPU
172 * register numbers. Index 0 is the SREG register: the initial
173 * value is all 0 but the interrupt bit (bit 7).
175 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
180 * Execute \a CODE atomically with respect to interrupts.
182 * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
184 #define ATOMIC(CODE) \
186 cpuflags_t __flags; \
187 DISABLE_IRQSAVE(__flags); \
189 ENABLE_IRQRESTORE(__flags); \
193 //! Default for macro not defined in the right arch section
194 #ifndef CPU_REG_INIT_VALUE
195 #define CPU_REG_INIT_VALUE(reg) 0
199 #ifndef CPU_STACK_GROWS_UPWARD
200 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
203 #ifndef CPU_SP_ON_EMPTY_SLOT
204 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
208 * Support stack handling peculiarities of a few CPUs.
210 * Most processors let their stack grow downward and
211 * keep SP pointing at the last pushed value.
213 #if !CPU_STACK_GROWS_UPWARD
214 #if !CPU_SP_ON_EMPTY_SLOT
215 /* Most microprocessors (x86, m68k...) */
216 #define CPU_PUSH_WORD(sp, data) \
217 do { *--(sp) = (data); } while (0)
218 #define CPU_POP_WORD(sp) \
222 #define CPU_PUSH_WORD(sp, data) \
223 do { *(sp)-- = (data); } while (0)
224 #define CPU_POP_WORD(sp) \
228 #else /* CPU_STACK_GROWS_UPWARD */
230 #if !CPU_SP_ON_EMPTY_SLOT
231 /* DSP56K and other weirdos */
232 #define CPU_PUSH_WORD(sp, data) \
233 do { *++(sp) = (cpustack_t)(data); } while (0)
234 #define CPU_POP_WORD(sp) \
237 #error I bet you cannot find a CPU like this
243 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
244 * RTS discards SR while returning (it does not restore it). So we push
245 * 0 to fake the same context.
247 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
249 CPU_PUSH_WORD((sp), (func)); \
250 CPU_PUSH_WORD((sp), 0x100); \
254 /* In AVR, the addresses are pushed into the stack as little-endian, while
255 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
256 * no natural endianess).
258 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
260 uint16_t funcaddr = (uint16_t)(func); \
261 CPU_PUSH_WORD((sp), funcaddr); \
262 CPU_PUSH_WORD((sp), funcaddr>>8); \
266 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
267 CPU_PUSH_WORD((sp), (func))
272 * \name Default type sizes
274 * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
275 * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
276 * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
278 * These defaults are reasonable for most 16/32bit machines.
279 * Some of these macros may be overridden by CPU-specific code above.
281 * ANSI C requires that the following equations be true:
283 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
284 * sizeof(float) <= sizeof(double)
285 * CPU_BITS_PER_CHAR >= 8
286 * CPU_BITS_PER_SHORT >= 8
287 * CPU_BITS_PER_INT >= 16
288 * CPU_BITS_PER_LONG >= 32
293 #define SIZEOF_CHAR 1
297 #define SIZEOF_SHORT 2
301 #if CPU_REG_BITS < 32
306 #endif /* !SIZEOF_INT */
309 #define SIZEOF_LONG 4
313 #define SIZEOF_PTR SIZEOF_INT
316 #ifndef CPU_BITS_PER_CHAR
317 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
320 #ifndef CPU_BITS_PER_SHORT
321 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
324 #ifndef CPU_BITS_PER_INT
325 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
328 #ifndef CPU_BITS_PER_LONG
329 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
332 #ifndef CPU_BITS_PER_PTR
333 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
337 /* Sanity checks for the above definitions */
338 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
339 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
340 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
341 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
345 * \def SCHEDULER_IDLE
347 * \brief Invoked by the scheduler to stop the CPU when idle.
349 * This hook can be redefined to put the CPU in low-power mode, or to
350 * profile system load with an external strobe, or to save CPU cycles
351 * in hosted environments such as emulators.
353 #ifndef SCHEDULER_IDLE
354 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
355 /* This emulator hook should yield the CPU to the host. */
357 void SchedulerIdle(void);
359 #define SCHEDULER_IDLE SchedulerIdle()
360 #else /* !ARCH_EMUL */
361 #define SCHEDULER_IDLE do { /* nothing */ } while (0)
362 #endif /* !ARCH_EMUL */
363 #endif /* !SCHEDULER_IDLE */
365 #endif /* DEVLIB_CPU_H */