4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.21 2004/11/16 21:34:25 bernie
21 *#* Commonize obsolete names for IRQ macros; Doxygen fixes.
23 *#* Revision 1.20 2004/11/16 20:33:32 bernie
24 *#* CPU_HARVARD: New macro.
26 *#* Revision 1.19 2004/10/03 20:43:54 bernie
27 *#* Fix Doxygen markup.
29 *#* Revision 1.18 2004/10/03 18:36:31 bernie
30 *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
32 *#* Revision 1.17 2004/09/06 21:48:27 bernie
33 *#* ATOMIC(): New macro.
35 *#* Revision 1.16 2004/08/29 21:58:33 bernie
36 *#* Rename BITS_PER_XYZ macros; Add sanity checks.
38 *#* Revision 1.15 2004/08/25 14:12:08 rasky
39 *#* Aggiornato il comment block dei log RCS
41 *#* Revision 1.14 2004/08/24 13:29:28 bernie
42 *#* Trim CVS log; Rename header guards.
44 *#* Revision 1.12 2004/08/14 19:37:57 rasky
45 *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
47 *#* Revision 1.11 2004/08/05 17:39:56 bernie
48 *#* Fix a Doxygen tag.
50 *#* Revision 1.10 2004/08/02 20:20:29 aleph
51 *#* Merge from project_ks
53 *#* Revision 1.9 2004/07/30 14:24:16 rasky
54 *#* Task switching con salvataggio perfetto stato di interrupt (SR)
55 *#* Kernel monitor per dump informazioni su stack dei processi
60 #include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
64 * \name Macros for determining CPU endianness.
67 #define CPU_BIG_ENDIAN 0x1234
68 #define CPU_LITTLE_ENDIAN 0x3412
71 /*! Macro to include cpu-specific versions of the headers. */
72 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
77 #define NOP nop_instruction()
78 #define IRQ_DISABLE disable_interrupt()
79 #define IRQ_ENABLE enable_interrupt()
81 typedef uint16_t cpuflags_t; // FIXME
82 typedef unsigned int cpustack_t;
84 #define CPU_REG_BITS 16
85 #define CPU_REGS_CNT 16
86 #define CPU_STACK_GROWS_UPWARD 0
87 #define CPU_SP_ON_EMPTY_SLOT 0
88 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
93 #define NOP asm volatile ("nop")
94 #define IRQ_DISABLE /* nothing */
95 #define IRQ_ENABLE /* nothing */
97 typedef uint32_t cpuflags_t; // FIXME
98 typedef uint32_t cpustack_t;
100 #define CPU_REG_BITS 32
101 #define CPU_REGS_CNT 7
102 #define CPU_STACK_GROWS_UPWARD 0
103 #define CPU_SP_ON_EMPTY_SLOT 0
104 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
105 #define CPU_HARVARD 0
110 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
111 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
113 #define IRQ_SAVE_DISABLE(x) \
114 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
115 #define IRQ_RESTORE(x) \
116 do { (void)x; asm(move x,SR); } while (0)
119 typedef uint16_t cpuflags_t;
120 typedef unsigned int cpustack_t;
122 #define CPU_REG_BITS 16
123 #define CPU_REGS_CNT FIXME
124 #define CPU_SAVED_REGS_CNT 8
125 #define CPU_STACK_GROWS_UPWARD 1
126 #define CPU_SP_ON_EMPTY_SLOT 0
127 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
129 /* Memory is word-addessed in the DSP56K */
130 #define CPU_BITS_PER_CHAR 16
131 #define SIZEOF_SHORT 1
133 #define SIZEOF_LONG 2
138 #define NOP asm volatile ("nop" ::)
139 #define IRQ_DISABLE asm volatile ("cli" ::)
140 #define IRQ_ENABLE asm volatile ("sei" ::)
142 #define IRQ_SAVE_DISABLE(x) \
144 __asm__ __volatile__( \
145 "in %0,__SREG__\n\t" \
147 : "=r" (x) : /* no inputs */ : "cc" \
151 #define IRQ_RESTORE(x) \
153 __asm__ __volatile__( \
154 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
158 #define IRQ_GETSTATE() \
161 __asm__ __volatile__( \
162 "in %0,__SREG__\n\t" \
163 : "=r" (sreg) /* no inputs & no clobbers */ \
165 (bool)(sreg & 0x80); \
168 typedef uint8_t cpuflags_t;
169 typedef uint8_t cpustack_t;
171 /* Register counts include SREG too */
172 #define CPU_REG_BITS 8
173 #define CPU_REGS_CNT 33
174 #define CPU_SAVED_REGS_CNT 19
175 #define CPU_STACK_GROWS_UPWARD 0
176 #define CPU_SP_ON_EMPTY_SLOT 1
177 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
180 * Initialization value for registers in stack frame.
181 * The register index is not directly corrispondent to CPU
182 * register numbers. Index 0 is the SREG register: the initial
183 * value is all 0 but the interrupt bit (bit 7).
185 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
190 #define DISABLE_INTS IRQ_DISABLE
191 #define ENABLE_INTS IRQ_ENABLE
192 #define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x)
193 #define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
196 * Execute \a CODE atomically with respect to interrupts.
198 * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
200 #define ATOMIC(CODE) \
202 cpuflags_t __flags; \
203 DISABLE_IRQSAVE(__flags); \
205 ENABLE_IRQRESTORE(__flags); \
209 //! Default for macro not defined in the right arch section
210 #ifndef CPU_REG_INIT_VALUE
211 #define CPU_REG_INIT_VALUE(reg) 0
215 #ifndef CPU_STACK_GROWS_UPWARD
216 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
219 #ifndef CPU_SP_ON_EMPTY_SLOT
220 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
224 * Support stack handling peculiarities of a few CPUs.
226 * Most processors let their stack grow downward and
227 * keep SP pointing at the last pushed value.
229 #if !CPU_STACK_GROWS_UPWARD
230 #if !CPU_SP_ON_EMPTY_SLOT
231 /* Most microprocessors (x86, m68k...) */
232 #define CPU_PUSH_WORD(sp, data) \
233 do { *--(sp) = (data); } while (0)
234 #define CPU_POP_WORD(sp) \
238 #define CPU_PUSH_WORD(sp, data) \
239 do { *(sp)-- = (data); } while (0)
240 #define CPU_POP_WORD(sp) \
244 #else /* CPU_STACK_GROWS_UPWARD */
246 #if !CPU_SP_ON_EMPTY_SLOT
247 /* DSP56K and other weirdos */
248 #define CPU_PUSH_WORD(sp, data) \
249 do { *++(sp) = (cpustack_t)(data); } while (0)
250 #define CPU_POP_WORD(sp) \
253 #error I bet you cannot find a CPU like this
260 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
261 * RTS discards SR while returning (it does not restore it). So we push
262 * 0 to fake the same context.
264 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
266 CPU_PUSH_WORD((sp), (func)); \
267 CPU_PUSH_WORD((sp), 0x100); \
272 * In AVR, the addresses are pushed into the stack as little-endian, while
273 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
274 * no natural endianess).
276 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
278 uint16_t funcaddr = (uint16_t)(func); \
279 CPU_PUSH_WORD((sp), funcaddr); \
280 CPU_PUSH_WORD((sp), funcaddr>>8); \
284 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
285 CPU_PUSH_WORD((sp), (func))
290 * \name Default type sizes
292 * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
293 * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
294 * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
296 * These defaults are reasonable for most 16/32bit machines.
297 * Some of these macros may be overridden by CPU-specific code above.
299 * ANSI C requires that the following equations be true:
301 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
302 * sizeof(float) <= sizeof(double)
303 * CPU_BITS_PER_CHAR >= 8
304 * CPU_BITS_PER_SHORT >= 8
305 * CPU_BITS_PER_INT >= 16
306 * CPU_BITS_PER_LONG >= 32
311 #define SIZEOF_CHAR 1
315 #define SIZEOF_SHORT 2
319 #if CPU_REG_BITS < 32
324 #endif /* !SIZEOF_INT */
327 #define SIZEOF_LONG 4
331 #define SIZEOF_PTR SIZEOF_INT
334 #ifndef CPU_BITS_PER_CHAR
335 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
338 #ifndef CPU_BITS_PER_SHORT
339 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
342 #ifndef CPU_BITS_PER_INT
343 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
346 #ifndef CPU_BITS_PER_LONG
347 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
350 #ifndef CPU_BITS_PER_PTR
351 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
355 /* Sanity checks for the above definitions */
356 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
357 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
358 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
359 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
363 * \def SCHEDULER_IDLE
365 * \brief Invoked by the scheduler to stop the CPU when idle.
367 * This hook can be redefined to put the CPU in low-power mode, or to
368 * profile system load with an external strobe, or to save CPU cycles
369 * in hosted environments such as emulators.
371 #ifndef SCHEDULER_IDLE
372 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
373 /* This emulator hook should yield the CPU to the host. */
375 void SchedulerIdle(void);
377 #define SCHEDULER_IDLE SchedulerIdle()
378 #else /* !ARCH_EMUL */
379 #define SCHEDULER_IDLE do { /* nothing */ } while (0)
380 #endif /* !ARCH_EMUL */
381 #endif /* !SCHEDULER_IDLE */
383 #endif /* DEVLIB_CPU_H */