4 * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.2 2005/04/11 19:10:27 bernie
21 *#* Include top-level headers from cfg/ subdir.
23 *#* Revision 1.1 2005/04/11 19:04:13 bernie
24 *#* Move top-level headers to cfg/ subdir.
26 *#* Revision 1.30 2005/03/15 00:20:09 bernie
27 *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
29 *#* Revision 1.29 2005/02/16 20:33:24 bernie
30 *#* Preliminary PPC support.
32 *#* Revision 1.28 2004/12/31 17:39:41 bernie
33 *#* Fix documentation.
35 *#* Revision 1.27 2004/12/31 17:02:47 bernie
36 *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
38 *#* Revision 1.26 2004/12/13 12:08:12 bernie
39 *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
41 *#* Revision 1.25 2004/12/08 08:31:02 bernie
42 *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
47 #include <cfg/compiler.h> /* for uintXX_t */
51 * \name Macros for determining CPU endianness.
54 #define CPU_BIG_ENDIAN 0x1234
55 #define CPU_LITTLE_ENDIAN 0x3412
58 /*! Macro to include cpu-specific versions of the headers. */
59 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
64 #define NOP nop_instruction()
65 #define IRQ_DISABLE disable_interrupt()
66 #define IRQ_ENABLE enable_interrupt()
68 typedef uint16_t cpuflags_t; // FIXME
69 typedef unsigned int cpustack_t;
71 #define CPU_REG_BITS 16
72 #define CPU_REGS_CNT 16
73 #define CPU_STACK_GROWS_UPWARD 0
74 #define CPU_SP_ON_EMPTY_SLOT 0
75 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
80 #define NOP asm volatile ("nop")
81 #define IRQ_DISABLE /* nothing */
82 #define IRQ_ENABLE /* nothing */
83 #define IRQ_SAVE_DISABLE(x) /* nothing */
84 #define IRQ_RESTORE(x) /* nothing */
86 typedef uint32_t cpuflags_t; // FIXME
87 typedef uint32_t cpustack_t;
89 #define CPU_REG_BITS 32
90 #define CPU_REGS_CNT 7
91 #define CPU_STACK_GROWS_UPWARD 0
92 #define CPU_SP_ON_EMPTY_SLOT 0
93 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
97 #define NOP asm volatile ("nop" ::)
98 #define IRQ_DISABLE FIXME
99 #define IRQ_ENABLE FIXME
100 #define IRQ_SAVE_DISABLE(x) FIXME
101 #define IRQ_RESTORE(x) FIXME
102 #define IRQ_GETSTATE() FIXME
104 typedef uint32_t cpuflags_t; // FIXME
105 typedef uint32_t cpustack_t; // FIXME
107 /* Register counts include SREG too */
108 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
109 #define CPU_REGS_CNT FIXME
110 #define CPU_SAVED_REGS_CNT FIXME
111 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
112 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
113 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
114 #define CPU_HARVARD 0
119 #define BREAKPOINT asm(debug)
120 #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
121 #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
123 #define IRQ_SAVE_DISABLE(x) \
124 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
125 #define IRQ_RESTORE(x) \
126 do { (void)x; asm(move x,SR); } while (0)
128 static inline bool irq_running(void)
130 extern void *user_sp;
133 #define IRQ_RUNNING() irq_running()
135 static inline bool irq_getstate(void)
139 return !(x & 0x0200);
141 #define IRQ_GETSTATE() irq_getstate()
145 typedef uint16_t cpuflags_t;
146 typedef unsigned int cpustack_t;
148 #define CPU_REG_BITS 16
149 #define CPU_REGS_CNT FIXME
150 #define CPU_SAVED_REGS_CNT 8
151 #define CPU_STACK_GROWS_UPWARD 1
152 #define CPU_SP_ON_EMPTY_SLOT 0
153 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
154 #define CPU_HARVARD 1
156 /* Memory is word-addessed in the DSP56K */
157 #define CPU_BITS_PER_CHAR 16
158 #define SIZEOF_SHORT 1
160 #define SIZEOF_LONG 2
165 #define NOP asm volatile ("nop" ::)
166 #define IRQ_DISABLE asm volatile ("cli" ::)
167 #define IRQ_ENABLE asm volatile ("sei" ::)
169 #define IRQ_SAVE_DISABLE(x) \
171 __asm__ __volatile__( \
172 "in %0,__SREG__\n\t" \
174 : "=r" (x) : /* no inputs */ : "cc" \
178 #define IRQ_RESTORE(x) \
180 __asm__ __volatile__( \
181 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
185 #define IRQ_GETSTATE() \
188 __asm__ __volatile__( \
189 "in %0,__SREG__\n\t" \
190 : "=r" (sreg) /* no inputs & no clobbers */ \
192 (bool)(sreg & 0x80); \
195 typedef uint8_t cpuflags_t;
196 typedef uint8_t cpustack_t;
198 /* Register counts include SREG too */
199 #define CPU_REG_BITS 8
200 #define CPU_REGS_CNT 33
201 #define CPU_SAVED_REGS_CNT 19
202 #define CPU_STACK_GROWS_UPWARD 0
203 #define CPU_SP_ON_EMPTY_SLOT 1
204 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
205 #define CPU_HARVARD 1
208 * Initialization value for registers in stack frame.
209 * The register index is not directly corrispondent to CPU
210 * register numbers. Index 0 is the SREG register: the initial
211 * value is all 0 but the interrupt bit (bit 7).
213 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
218 * Execute \a CODE atomically with respect to interrupts.
220 * \see IRQ_SAVE_DISABLE IRQ_RESTORE
222 #define ATOMIC(CODE) \
224 cpuflags_t __flags; \
225 IRQ_SAVE_DISABLE(__flags); \
227 IRQ_RESTORE(__flags); \
231 //! Default for macro not defined in the right arch section
232 #ifndef CPU_REG_INIT_VALUE
233 #define CPU_REG_INIT_VALUE(reg) 0
237 #ifndef CPU_STACK_GROWS_UPWARD
238 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
241 #ifndef CPU_SP_ON_EMPTY_SLOT
242 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
246 * Support stack handling peculiarities of a few CPUs.
248 * Most processors let their stack grow downward and
249 * keep SP pointing at the last pushed value.
251 #if !CPU_STACK_GROWS_UPWARD
252 #if !CPU_SP_ON_EMPTY_SLOT
253 /* Most microprocessors (x86, m68k...) */
254 #define CPU_PUSH_WORD(sp, data) \
255 do { *--(sp) = (data); } while (0)
256 #define CPU_POP_WORD(sp) \
260 #define CPU_PUSH_WORD(sp, data) \
261 do { *(sp)-- = (data); } while (0)
262 #define CPU_POP_WORD(sp) \
266 #else /* CPU_STACK_GROWS_UPWARD */
268 #if !CPU_SP_ON_EMPTY_SLOT
269 /* DSP56K and other weirdos */
270 #define CPU_PUSH_WORD(sp, data) \
271 do { *++(sp) = (cpustack_t)(data); } while (0)
272 #define CPU_POP_WORD(sp) \
275 #error I bet you cannot find a CPU like this
282 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
283 * RTS discards SR while returning (it does not restore it). So we push
284 * 0 to fake the same context.
286 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
288 CPU_PUSH_WORD((sp), (func)); \
289 CPU_PUSH_WORD((sp), 0x100); \
294 * In AVR, the addresses are pushed into the stack as little-endian, while
295 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
296 * no natural endianess).
298 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
300 uint16_t funcaddr = (uint16_t)(func); \
301 CPU_PUSH_WORD((sp), funcaddr); \
302 CPU_PUSH_WORD((sp), funcaddr>>8); \
306 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
307 CPU_PUSH_WORD((sp), (func))
312 * \name Default type sizes.
314 * These defaults are reasonable for most 16/32bit machines.
315 * Some of these macros may be overridden by CPU-specific code above.
317 * ANSI C requires that the following equations be true:
319 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
320 * sizeof(float) <= sizeof(double)
321 * CPU_BITS_PER_CHAR >= 8
322 * CPU_BITS_PER_SHORT >= 8
323 * CPU_BITS_PER_INT >= 16
324 * CPU_BITS_PER_LONG >= 32
329 #define SIZEOF_CHAR 1
333 #define SIZEOF_SHORT 2
337 #if CPU_REG_BITS < 32
342 #endif /* !SIZEOF_INT */
345 #if CPU_REG_BITS > 32
346 #define SIZEOF_LONG 8
348 #define SIZEOF_LONG 4
353 #define SIZEOF_PTR SIZEOF_INT
356 #ifndef CPU_BITS_PER_CHAR
357 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
360 #ifndef CPU_BITS_PER_SHORT
361 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
364 #ifndef CPU_BITS_PER_INT
365 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
368 #ifndef CPU_BITS_PER_LONG
369 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
372 #ifndef CPU_BITS_PER_PTR
373 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
377 #define BREAKPOINT /* nop */
382 /* Sanity checks for the above definitions */
383 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
384 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
385 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
386 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
392 * \brief Invoked by the scheduler to stop the CPU when idle.
394 * This hook can be redefined to put the CPU in low-power mode, or to
395 * profile system load with an external strobe, or to save CPU cycles
396 * in hosted environments such as emulators.
399 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
400 /* This emulator hook should yield the CPU to the host. */
402 void SchedulerIdle(void);
404 #define CPU_IDLE SchedulerIdle()
405 #else /* !ARCH_EMUL */
406 #define CPU_IDLE do { /* nothing */ } while (0)
407 #endif /* !ARCH_EMUL */
408 #endif /* !CPU_IDLE */
411 #define SCHEDULER_IDLE CPU_IDLE
413 #endif /* DEVLIB_CPU_H */