4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 * Revision 1.12 2004/08/14 19:37:57 rasky
21 * Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
23 * Revision 1.11 2004/08/05 17:39:56 bernie
26 * Revision 1.10 2004/08/02 20:20:29 aleph
27 * Merge from project_ks
29 * Revision 1.9 2004/07/30 14:24:16 rasky
30 * Task switching con salvataggio perfetto stato di interrupt (SR)
31 * Kernel monitor per dump informazioni su stack dei processi
33 * Revision 1.8 2004/07/30 14:15:53 rasky
34 * Nuovo supporto unificato per detect della CPU
36 * Revision 1.7 2004/07/20 23:26:48 bernie
37 * Fix two errors introduced by previous commit.
39 * Revision 1.6 2004/07/20 23:12:16 bernie
40 * Rationalize and document SCHEDULER_IDLE.
42 * Revision 1.5 2004/07/20 16:20:35 bernie
43 * Move byte-order macros to mware/byteorder.h; Add missing author names.
45 * Revision 1.4 2004/07/20 16:06:04 bernie
46 * Add macros to handle endianess issues.
48 * Revision 1.3 2004/07/18 21:49:51 bernie
51 * Revision 1.2 2004/06/03 11:27:09 bernie
52 * Add dual-license information.
54 * Revision 1.1 2004/05/23 17:48:35 bernie
55 * Add top-level files.
64 // Macros for determining CPU endianness
65 #define CPU_BIG_ENDIAN 0x1234
66 #define CPU_LITTLE_ENDIAN 0x3412
68 // Macros to include cpu-specific version of the headers
69 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
74 #define DISABLE_INTS disable_interrupt()
75 #define ENABLE_INTS enable_interrupt()
76 #define NOP nop_instruction()
78 typedef uint16_t cpuflags_t; // FIXME
79 typedef unsigned int cpustack_t;
81 #define CPU_REGS_CNT 16
82 #define CPU_STACK_GROWS_UPWARD 0
83 #define CPU_SP_ON_EMPTY_SLOT 0
84 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
88 #define NOP asm volatile ("nop")
89 #define DISABLE_INTS /* nothing */
90 #define ENABLE_INTS /* nothing */
92 typedef uint32_t cpuflags_t; // FIXME
93 typedef uint32_t cpustack_t;
95 #define CPU_REGS_CNT 7
96 #define CPU_STACK_GROWS_UPWARD 0
97 #define CPU_SP_ON_EMPTY_SLOT 0
98 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
103 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
104 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
106 #define DISABLE_IRQSAVE(x) \
107 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
108 #define ENABLE_IRQRESTORE(x) \
109 do { (void)x; asm(move x,SR); } while (0)
111 typedef uint16_t cpuflags_t;
112 typedef unsigned int cpustack_t;
114 #define CPU_REGS_CNT FIXME
115 #define CPU_SAVED_REGS_CNT 8
116 #define CPU_STACK_GROWS_UPWARD 1
117 #define CPU_SP_ON_EMPTY_SLOT 0
118 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
122 #define NOP asm volatile ("nop" ::)
123 #define DISABLE_INTS asm volatile ("cli" ::)
124 #define ENABLE_INTS asm volatile ("sei" ::)
126 #define DISABLE_IRQSAVE(x) \
128 __asm__ __volatile__( \
129 "in %0,__SREG__\n\t" \
131 : "=r" (x) : /* no inputs */ : "cc" \
135 #define ENABLE_IRQRESTORE(x) \
137 __asm__ __volatile__( \
138 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
142 typedef uint8_t cpuflags_t;
143 typedef uint8_t cpustack_t;
145 /* Register counts include SREG too */
146 #define CPU_REGS_CNT 33
147 #define CPU_SAVED_REGS_CNT 19
148 #define CPU_STACK_GROWS_UPWARD 0
149 #define CPU_SP_ON_EMPTY_SLOT 1
150 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
153 * Initialization value for registers in stack frame.
154 * The register index is not directly corrispondent to CPU
155 * register numbers. Index 0 is the SREG register: the initial
156 * value is all 0 but the interrupt bit (bit 7).
158 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
163 //! Default for macro not defined in the right arch section
164 #ifndef CPU_REG_INIT_VALUE
165 #define CPU_REG_INIT_VALUE(reg) 0
169 #ifndef CPU_STACK_GROWS_UPWARD
170 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
173 #ifndef CPU_SP_ON_EMPTY_SLOT
174 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
178 * Support stack handling peculiarities of a few CPUs.
180 * Most processors let their stack grow downward and
181 * keep SP pointing at the last pushed value.
183 #if !CPU_STACK_GROWS_UPWARD
184 #if !CPU_SP_ON_EMPTY_SLOT
185 /* Most microprocessors (x86, m68k...) */
186 #define CPU_PUSH_WORD(sp, data) \
187 do { *--(sp) = (data); } while (0)
188 #define CPU_POP_WORD(sp) \
192 #define CPU_PUSH_WORD(sp, data) \
193 do { *(sp)-- = (data); } while (0)
194 #define CPU_POP_WORD(sp) \
198 #else /* CPU_STACK_GROWS_UPWARD */
200 #if !CPU_SP_ON_EMPTY_SLOT
201 /* DSP56K and other weirdos */
202 #define CPU_PUSH_WORD(sp, data) \
203 do { *++(sp) = (cpustack_t)(data); } while (0)
204 #define CPU_POP_WORD(sp) \
207 #error I bet you cannot find a CPU like this
213 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
214 * RTS discards SR while returning (it does not restore it). So we push
215 * 0 to fake the same context.
217 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
219 CPU_PUSH_WORD((sp), (func)); \
220 CPU_PUSH_WORD((sp), 0x100); \
224 /* In AVR, the addresses are pushed into the stack as little-endian, while
225 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
226 * no natural endianess).
228 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
230 uint16_t funcaddr = (uint16_t)(func); \
231 CPU_PUSH_WORD((sp), funcaddr); \
232 CPU_PUSH_WORD((sp), funcaddr>>8); \
236 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
237 CPU_PUSH_WORD((sp), (func))
242 * \def SCHEDULER_IDLE
244 * \brief Invoked by the scheduler to stop the CPU when idle.
246 * This hook can be redefined to put the CPU in low-power mode, or to
247 * profile system load with an external strobe, or to save CPU cycles
248 * in hosted environments such as emulators.
250 #ifndef SCHEDULER_IDLE
251 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
252 /* This emulator hook should yield the CPU to the host. */
254 void SchedulerIdle(void);
256 #else /* !ARCH_EMUL */
257 #define SCHEDULER_IDLE /* nothing */
258 #endif /* !ARCH_EMUL */
259 #endif /* !SCHEDULER_IDLE */