4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
14 * \author Bernardo Innocenti <bernie@develer.com>
15 * \author Stefano Fedrigo <aleph@develer.com>
20 *#* Revision 1.19 2004/10/03 20:43:54 bernie
21 *#* Fix Doxygen markup.
23 *#* Revision 1.18 2004/10/03 18:36:31 bernie
24 *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
26 *#* Revision 1.17 2004/09/06 21:48:27 bernie
27 *#* ATOMIC(): New macro.
29 *#* Revision 1.16 2004/08/29 21:58:33 bernie
30 *#* Rename BITS_PER_XYZ macros; Add sanity checks.
32 *#* Revision 1.15 2004/08/25 14:12:08 rasky
33 *#* Aggiornato il comment block dei log RCS
35 *#* Revision 1.14 2004/08/24 13:29:28 bernie
36 *#* Trim CVS log; Rename header guards.
38 *#* Revision 1.12 2004/08/14 19:37:57 rasky
39 *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
41 *#* Revision 1.11 2004/08/05 17:39:56 bernie
42 *#* Fix a Doxygen tag.
44 *#* Revision 1.10 2004/08/02 20:20:29 aleph
45 *#* Merge from project_ks
47 *#* Revision 1.9 2004/07/30 14:24:16 rasky
48 *#* Task switching con salvataggio perfetto stato di interrupt (SR)
49 *#* Kernel monitor per dump informazioni su stack dei processi
54 #include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
57 // Macros for determining CPU endianness
58 #define CPU_BIG_ENDIAN 0x1234
59 #define CPU_LITTLE_ENDIAN 0x3412
61 // Macros to include cpu-specific version of the headers
62 #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
67 #define DISABLE_INTS disable_interrupt()
68 #define ENABLE_INTS enable_interrupt()
69 #define NOP nop_instruction()
71 typedef uint16_t cpuflags_t; // FIXME
72 typedef unsigned int cpustack_t;
74 #define CPU_REG_BITS 16
75 #define CPU_REGS_CNT 16
76 #define CPU_STACK_GROWS_UPWARD 0
77 #define CPU_SP_ON_EMPTY_SLOT 0
78 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
82 #define NOP asm volatile ("nop")
83 #define DISABLE_INTS /* nothing */
84 #define ENABLE_INTS /* nothing */
86 typedef uint32_t cpuflags_t; // FIXME
87 typedef uint32_t cpustack_t;
89 #define CPU_REG_BITS 32
90 #define CPU_REGS_CNT 7
91 #define CPU_STACK_GROWS_UPWARD 0
92 #define CPU_SP_ON_EMPTY_SLOT 0
93 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
98 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
99 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
101 #define DISABLE_IRQSAVE(x) \
102 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
103 #define ENABLE_IRQRESTORE(x) \
104 do { (void)x; asm(move x,SR); } while (0)
106 typedef uint16_t cpuflags_t;
107 typedef unsigned int cpustack_t;
109 #define CPU_REG_BITS 16
110 #define CPU_REGS_CNT FIXME
111 #define CPU_SAVED_REGS_CNT 8
112 #define CPU_STACK_GROWS_UPWARD 1
113 #define CPU_SP_ON_EMPTY_SLOT 0
114 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
116 /* Memory is word-addessed in the DSP56K */
117 #define CPU_BITS_PER_CHAR 16
118 #define SIZEOF_SHORT 1
120 #define SIZEOF_LONG 2
125 #define NOP asm volatile ("nop" ::)
126 #define IRQ_DISABLE asm volatile ("cli" ::)
127 #define IRQ_ENABLE asm volatile ("sei" ::)
129 #define IRQ_SAVE_DISABLE(x) \
131 __asm__ __volatile__( \
132 "in %0,__SREG__\n\t" \
134 : "=r" (x) : /* no inputs */ : "cc" \
138 #define IRQ_RESTORE(x) \
140 __asm__ __volatile__( \
141 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
145 #define IRQ_GETSTATE() \
148 __asm__ __volatile__( \
149 "in %0,__SREG__\n\t" \
150 : "=r" (sreg) /* no inputs & no clobbers */ \
152 (bool)(sreg & 0x80); \
156 #define DISABLE_INTS IRQ_DISABLE
157 #define ENABLE_INTS IRQ_ENABLE
158 #define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x)
159 #define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
161 typedef uint8_t cpuflags_t;
162 typedef uint8_t cpustack_t;
164 /* Register counts include SREG too */
165 #define CPU_REG_BITS 8
166 #define CPU_REGS_CNT 33
167 #define CPU_SAVED_REGS_CNT 19
168 #define CPU_STACK_GROWS_UPWARD 0
169 #define CPU_SP_ON_EMPTY_SLOT 1
170 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
173 * Initialization value for registers in stack frame.
174 * The register index is not directly corrispondent to CPU
175 * register numbers. Index 0 is the SREG register: the initial
176 * value is all 0 but the interrupt bit (bit 7).
178 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
183 * Execute \a CODE atomically with respect to interrupts.
185 * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
187 #define ATOMIC(CODE) \
189 cpuflags_t __flags; \
190 DISABLE_IRQSAVE(__flags); \
192 ENABLE_IRQRESTORE(__flags); \
196 //! Default for macro not defined in the right arch section
197 #ifndef CPU_REG_INIT_VALUE
198 #define CPU_REG_INIT_VALUE(reg) 0
202 #ifndef CPU_STACK_GROWS_UPWARD
203 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
206 #ifndef CPU_SP_ON_EMPTY_SLOT
207 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
211 * Support stack handling peculiarities of a few CPUs.
213 * Most processors let their stack grow downward and
214 * keep SP pointing at the last pushed value.
216 #if !CPU_STACK_GROWS_UPWARD
217 #if !CPU_SP_ON_EMPTY_SLOT
218 /* Most microprocessors (x86, m68k...) */
219 #define CPU_PUSH_WORD(sp, data) \
220 do { *--(sp) = (data); } while (0)
221 #define CPU_POP_WORD(sp) \
225 #define CPU_PUSH_WORD(sp, data) \
226 do { *(sp)-- = (data); } while (0)
227 #define CPU_POP_WORD(sp) \
231 #else /* CPU_STACK_GROWS_UPWARD */
233 #if !CPU_SP_ON_EMPTY_SLOT
234 /* DSP56K and other weirdos */
235 #define CPU_PUSH_WORD(sp, data) \
236 do { *++(sp) = (cpustack_t)(data); } while (0)
237 #define CPU_POP_WORD(sp) \
240 #error I bet you cannot find a CPU like this
246 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
247 * RTS discards SR while returning (it does not restore it). So we push
248 * 0 to fake the same context.
250 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
252 CPU_PUSH_WORD((sp), (func)); \
253 CPU_PUSH_WORD((sp), 0x100); \
257 /* In AVR, the addresses are pushed into the stack as little-endian, while
258 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
259 * no natural endianess).
261 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
263 uint16_t funcaddr = (uint16_t)(func); \
264 CPU_PUSH_WORD((sp), funcaddr); \
265 CPU_PUSH_WORD((sp), funcaddr>>8); \
269 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
270 CPU_PUSH_WORD((sp), (func))
275 * \name Default type sizes
277 * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
278 * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
279 * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
281 * These defaults are reasonable for most 16/32bit machines.
282 * Some of these macros may be overridden by CPU-specific code above.
284 * ANSI C requires that the following equations be true:
286 * sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
287 * sizeof(float) <= sizeof(double)
288 * CPU_BITS_PER_CHAR >= 8
289 * CPU_BITS_PER_SHORT >= 8
290 * CPU_BITS_PER_INT >= 16
291 * CPU_BITS_PER_LONG >= 32
296 #define SIZEOF_CHAR 1
300 #define SIZEOF_SHORT 2
304 #if CPU_REG_BITS < 32
309 #endif /* !SIZEOF_INT */
312 #define SIZEOF_LONG 4
316 #define SIZEOF_PTR SIZEOF_INT
319 #ifndef CPU_BITS_PER_CHAR
320 #define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
323 #ifndef CPU_BITS_PER_SHORT
324 #define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
327 #ifndef CPU_BITS_PER_INT
328 #define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
331 #ifndef CPU_BITS_PER_LONG
332 #define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
335 #ifndef CPU_BITS_PER_PTR
336 #define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
340 /* Sanity checks for the above definitions */
341 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
342 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
343 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
344 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
348 * \def SCHEDULER_IDLE
350 * \brief Invoked by the scheduler to stop the CPU when idle.
352 * This hook can be redefined to put the CPU in low-power mode, or to
353 * profile system load with an external strobe, or to save CPU cycles
354 * in hosted environments such as emulators.
356 #ifndef SCHEDULER_IDLE
357 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
358 /* This emulator hook should yield the CPU to the host. */
360 void SchedulerIdle(void);
362 #define SCHEDULER_IDLE SchedulerIdle()
363 #else /* !ARCH_EMUL */
364 #define SCHEDULER_IDLE do { /* nothing */ } while (0)
365 #endif /* !ARCH_EMUL */
366 #endif /* !SCHEDULER_IDLE */
368 #endif /* DEVLIB_CPU_H */