4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
18 * Revision 1.4 2004/07/20 16:06:04 bernie
19 * Add macros to handle endianess issues.
21 * Revision 1.3 2004/07/18 21:49:51 bernie
24 * Revision 1.2 2004/06/03 11:27:09 bernie
25 * Add dual-license information.
27 * Revision 1.1 2004/05/23 17:48:35 bernie
28 * Add top-level files.
36 //! Initialization value for registers in stack frame
37 #define CPU_REG_INIT_VALUE(reg) 0
39 // Macros for determining CPU endianness
40 #define CPU_BIG_ENDIAN 0x1234
41 #define CPU_LITTLE_ENDIAN 0x3412
44 #if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__) /* 80C196 */
46 #define DISABLE_INTS disable_interrupt()
47 #define ENABLE_INTS enable_interrupt()
48 #define NOP nop_instruction()
49 #define SCHEDULER_IDLE /* Hmmm... could we go in STOP mode? */
51 typedef uint16_t cpuflags_t; // FIXME
52 typedef unsigned int cpustack_t;
54 #define CPU_REGS_CNT 16
55 #define CPU_STACK_GROWS_UPWARD 0
56 #define CPU_SP_ON_EMPTY_SLOT 0
57 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
59 #elif defined(__i386__) || defined(_MSC_VER) /* x86 */
61 #define NOP asm volatile ("nop")
62 #define DISABLE_INTS /* nothing */
63 #define ENABLE_INTS /* nothing */
64 #define SCHEDULER_IDLE SchedulerIdle()
66 typedef uint32_t cpuflags_t; // FIXME
67 typedef uint32_t cpustack_t;
69 #define CPU_REGS_CNT 7
70 #define CPU_STACK_GROWS_UPWARD 0
71 #define CPU_SP_ON_EMPTY_SLOT 0
72 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
74 #elif defined(__m56800E__) || defined(__m56800__) /* DSP56K */
77 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
78 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
79 #define SCHEDULER_IDLE /* nothing */
81 #define DISABLE_IRQSAVE(x) \
82 do { asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
83 #define ENABLE_IRQRESTORE(x) \
84 do { asm(move x,SR); } while (0)
86 typedef uint16_t cpuflags_t;
87 typedef unsigned int cpustack_t;
89 #define CPU_REGS_CNT FIXME
90 #define CPU_SAVED_REGS_CNT 28
91 #define CPU_STACK_GROWS_UPWARD 1
92 #define CPU_SP_ON_EMPTY_SLOT 0
93 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
95 #undef CPU_REG_INIT_VALUE
96 INLINE uint16_t CPU_REG_INIT_VALUE(int reg)
101 asm(move OMR, omr_img);
102 return omr_img & (BV(3)/*EX*/ | BV(1)/*MB*/ | BV(0)/*MA*/);
104 else if (reg == 16)/*M01*/
109 #elif defined (__AVR__)
111 #define NOP asm volatile ("nop" ::)
112 #define DISABLE_INTS asm volatile ("cli" ::)
113 #define ENABLE_INTS asm volatile ("sei" ::)
114 #define SCHEDULER_IDLE /* nothing */
116 #define DISABLE_IRQSAVE(x) \
118 __asm__ __volatile__( \
119 "in %0,__SREG__\n\t" \
121 : "=r" (x) : /* no inputs */ : "cc" \
125 #define ENABLE_IRQRESTORE(x) \
127 __asm__ __volatile__( \
128 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
132 typedef uint8_t cpuflags_t;
133 typedef uint8_t cpustack_t;
135 #define CPU_REGS_CNT 32
136 #define CPU_SAVED_REGS_CNT 18
137 #define CPU_STACK_GROWS_UPWARD 0
138 #define CPU_SP_ON_EMPTY_SLOT 1
139 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
145 #ifndef CPU_STACK_GROWS_UPWARD
146 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
149 #ifndef CPU_SP_ON_EMPTY_SLOT
150 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
154 * Support stack handling peculiarities of a few CPUs.
156 * Most processors let their stack grow downward and
157 * keep SP pointing at the last pushed value.
159 #if !CPU_STACK_GROWS_UPWARD
160 #if !CPU_SP_ON_EMPTY_SLOT
161 /* Most microprocessors (x86, m68k...) */
162 #define CPU_PUSH_WORD(sp, data) \
163 do { *--(sp) = (data); } while (0)
164 #define CPU_POP_WORD(sp) \
168 #define CPU_PUSH_WORD(sp, data) \
169 do { *(sp)-- = (data); } while (0)
170 #define CPU_POP_WORD(sp) \
174 #else /* CPU_STACK_GROWS_UPWARD */
176 #if !CPU_SP_ON_EMPTY_SLOT
177 /* DSP56K and other weirdos */
178 #define CPU_PUSH_WORD(sp, data) \
179 do { *++(sp) = (cpustack_t)(data); } while (0)
180 #define CPU_POP_WORD(sp) \
183 #error I bet you cannot find a CPU like this
188 #if defined(__m56800E__) || defined(__m56800__)
189 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
190 * RTS discards SR while returning (it does not restore it). So we push
191 * 0 to fake the same context.
193 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
195 CPU_PUSH_WORD((sp), (func)); \
196 CPU_PUSH_WORD((sp), 0); \
199 #elif defined (__AVR__)
200 /* In AVR, the addresses are pushed into the stack as little-endian, while
201 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
202 * no natural endianess).
204 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
206 uint16_t funcaddr = (uint16_t)(func); \
207 CPU_PUSH_WORD((sp), funcaddr); \
208 CPU_PUSH_WORD((sp), funcaddr>>8); \
212 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
213 CPU_PUSH_WORD((sp), (func))
217 INLINE uint16_t htobe16(uint16_t n);
218 INLINE uint16_t htobe16(uint16_t n)
220 if (CPU_BYTE_ORDER == CPU_LITTLE_ENDIAN)
226 INLINE uint16_t htole16(uint16_t n);
227 INLINE uint16_t htole16(uint16_t n)
229 if (CPU_BYTE_ORDER == CPU_BIG_ENDIAN)