4 * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2004 Giovanni Bajo
9 * \brief CPU-specific definitions
13 * \author Giovanni Bajo <rasky@develer.com>
18 * Revision 1.1 2004/05/23 17:48:35 bernie
19 * Add top-level files.
27 //! Initialization value for registers in stack frame
28 #define CPU_REG_INIT_VALUE(reg) 0
30 #if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__) /* 80C196 */
32 #define DISABLE_INTS disable_interrupt()
33 #define ENABLE_INTS enable_interrupt()
34 #define NOP nop_instruction()
35 #define SCHEDULER_IDLE /* Hmmm... could we go in STOP mode? */
37 typedef uint16_t cpuflags_t; // FIXME
38 typedef unsigned int cpustack_t;
40 #define CPU_REGS_CNT 16
41 #define CPU_STACK_GROWS_UPWARD 0
42 #define CPU_SP_ON_EMPTY_SLOT 0
44 #elif defined(__i386__) || defined(_MSC_VER) /* x86 */
46 #define NOP asm volatile ("nop")
47 #define DISABLE_INTS /* nothing */
48 #define ENABLE_INTS /* nothing */
49 #define SCHEDULER_IDLE SchedulerIdle()
51 typedef uint32_t cpuflags_t; // FIXME
52 typedef uint32_t cpustack_t;
54 #define CPU_REGS_CNT 7
55 #define CPU_STACK_GROWS_UPWARD 0
56 #define CPU_SP_ON_EMPTY_SLOT 0
58 #elif defined(__m56800E__) || defined(__m56800__) /* DSP56K */
61 #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
62 #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
63 #define SCHEDULER_IDLE /* nothing */
65 #define DISABLE_IRQSAVE(x) \
66 do { asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
67 #define ENABLE_IRQRESTORE(x) \
68 do { asm(move x,SR); } while (0)
70 typedef uint16_t cpuflags_t;
71 typedef unsigned int cpustack_t;
73 #define CPU_REGS_CNT FIXME
74 #define CPU_SAVED_REGS_CNT 28
75 #define CPU_STACK_GROWS_UPWARD 1
76 #define CPU_SP_ON_EMPTY_SLOT 0
78 #undef CPU_REG_INIT_VALUE
79 INLINE uint16_t CPU_REG_INIT_VALUE(int reg)
84 asm(move OMR, omr_img);
85 return omr_img & (BV(3)/*EX*/ | BV(1)/*MB*/ | BV(0)/*MA*/);
87 else if (reg == 16)/*M01*/
92 #elif defined (__AVR__)
94 #define NOP asm volatile ("nop")
95 #define DISABLE_INTS cli()
96 #define ENABLE_INTS sei()
97 #define SCHEDULER_IDLE /* nothing */
99 #define DISABLE_IRQSAVE(x) \
101 __asm__ __volatile__( \
102 "in %0,__SREG__\n\t" \
104 : "=r" (x) : /* no inputs */ : "cc" \
108 #define ENABLE_IRQRESTORE(x) \
110 __asm__ __volatile__( \
111 "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
115 typedef uint8_t cpuflags_t;
116 typedef uint8_t cpustack_t;
118 #define CPU_REGS_CNT 32
119 #define CPU_SAVED_REGS_CNT 18
120 #define CPU_STACK_GROWS_UPWARD 0
121 #define CPU_SP_ON_EMPTY_SLOT 1
128 #ifndef CPU_STACK_GROWS_UPWARD
129 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
132 #ifndef CPU_SP_ON_EMPTY_SLOT
133 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
137 * Support stack handling peculiarities of a few CPUs.
139 * Most processors let their stack grow downward and
140 * keep SP pointing at the last pushed value.
142 #if !CPU_STACK_GROWS_UPWARD
143 #if !CPU_SP_ON_EMPTY_SLOT
144 /* Most microprocessors (x86, m68k...) */
145 #define CPU_PUSH_WORD(sp, data) \
146 do { *--(sp) = (data); } while (0)
147 #define CPU_POP_WORD(sp) \
151 #define CPU_PUSH_WORD(sp, data) \
152 do { *(sp)-- = (data); } while (0)
153 #define CPU_POP_WORD(sp) \
157 #else /* CPU_STACK_GROWS_UPWARD */
159 #if !CPU_SP_ON_EMPTY_SLOT
160 /* DSP56K and other weirdos */
161 #define CPU_PUSH_WORD(sp, data) \
162 do { *++(sp) = (cpustack_t)(data); } while (0)
163 #define CPU_POP_WORD(sp) \
166 #error I bet you cannot find a CPU like this
171 #if defined(__m56800E__) || defined(__m56800__)
172 /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
173 * RTS discards SR while returning (it does not restore it). So we push
174 * 0 to fake the same context.
176 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
178 CPU_PUSH_WORD((sp), (func)); \
179 CPU_PUSH_WORD((sp), 0); \
182 #elif defined (__AVR__)
183 /* In AVR, the addresses are pushed into the stack as little-endian, while
184 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
185 * no natural endianess).
187 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
189 uint16_t funcaddr = (uint16_t)(func); \
190 CPU_PUSH_WORD((sp), funcaddr); \
191 CPU_PUSH_WORD((sp), funcaddr>>8); \
195 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
196 CPU_PUSH_WORD((sp), (func))