4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief ADC hardware-specific implementation
35 * \author Daniele Basile <asterix@develer.com>
41 #include "cfg/cfg_adc.h"
43 #include <cfg/macros.h>
44 #include <cfg/compiler.h>
46 // Define log settings for cfg/log.h.
47 #define LOG_LEVEL ADC_LOG_LEVEL
48 #define LOG_FORMAT ADC_LOG_FORMAT
52 #include <drv/irq_cm3.h>
56 #include <mware/event.h>
61 /* We use event to signal the end of conversion */
62 static Event data_ready;
63 /* The last converted data */
69 * The interrupt is connected to ready data, so when the
70 * adc ends the conversion we generate an event and then
71 * we return the converted value.
73 * \note to clear the Ready data bit and End of conversion
74 * bit we should read the Last Converted Data register, otherwise
75 * the ready data interrupt loop on this call.
77 static DECLARE_ISR(adc_conversion_end_irq)
80 if (ADC_ISR & BV(ADC_DRDY))
83 event_do(&data_ready);
88 * Select mux channel \a ch.
90 void adc_hw_select_ch(uint8_t ch)
92 /* Disable all channels */
93 ADC_CHDR = ADC_CH_MASK;
94 /* Enable select channel */
99 * Start an ADC convertion.
101 uint16_t adc_hw_read(void)
103 ADC_CR = BV(ADC_START);
104 event_wait(&data_ready);
111 void adc_hw_init(void)
113 /* Make sure that interrupt are enabled */
114 IRQ_ASSERT_ENABLED();
116 /* Initialize the dataready event */
117 event_initGeneric(&data_ready);
119 /* Clock ADC peripheral */
120 pmc_periphEnable(ADC_ID);
122 /* Reset adc controller */
126 * Set adc mode register:
127 * - Disable hardware trigger and enable software trigger.
128 * - Select normal mode.
132 /* Set ADC_BITS bit convertion resolution. */
134 ADC_MR &= ~BV(ADC_LOWRES);
136 ADC_MR |= BV(ADC_LOWRES);
138 #error No select bit resolution is supported to this CPU
142 LOG_INFO("Computed ADC_CLOCK %ld\n", ADC_CLOCK);
143 ADC_MR |= ((ADC_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
144 LOG_INFO("prescaler[%ld]\n", ADC_PRESCALER);
145 ADC_MR |= ((CONFIG_ADC_SUT << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
146 LOG_INFO("starup[%d]\n", CONFIG_ADC_SUT);
147 ADC_MR |= ((CONFIG_ADC_STTLING << ADC_SETTLING_SHIFT) & ADC_SETTLING_MASK);
148 LOG_INFO("sttime[%d]\n", CONFIG_ADC_STTLING);
149 ADC_MR |= ((CONFIG_ADC_TRACKTIM << ADC_TRACKTIM_SHIFT) & ADC_TRACKTIM_MASK);
150 LOG_INFO("tracking[%d]\n", CONFIG_ADC_TRACKTIM);
151 ADC_MR |= ((CONFIG_ADC_TRANSFER << ADC_TRANSFER_SHIFT) & ADC_TRANSFER_MASK);
152 LOG_INFO("tranfer[%d]\n", CONFIG_ADC_TRANSFER);
154 /* Register and enable irq for adc. */
155 sysirq_setHandler(INT_ADC, adc_conversion_end_irq);
156 ADC_IER = BV(ADC_DRDY);