4 * This file is part of BeRTOS.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief ADC hardware-specific implementation
35 * \author Daniele Basile <asterix@develer.com>
41 #include "cfg/cfg_adc.h"
43 #include <cfg/macros.h>
44 #include <cfg/compiler.h>
46 // Define log settings for cfg/log.h.
47 #define LOG_LEVEL ADC_LOG_LEVEL
48 #define LOG_FORMAT ADC_LOG_FORMAT
52 #include <drv/irq_cm3.h>
56 #include <mware/event.h>
61 /* We use event to signal the end of conversion */
62 static Event adc_data_ready;
63 /* The last converted data */
69 * The interrupt is connected to ready data, so when the
70 * adc ends the conversion we generate an event and then
71 * we return the converted value.
73 * \note to clear the Ready data bit and End of conversion
74 * bit we should read the Last Converted Data register, otherwise
75 * the ready data interrupt loop on this call.
77 static DECLARE_ISR(adc_conversion_end_irq)
79 if (ADC_ISR & BV(ADC_DRDY))
82 event_do(&adc_data_ready);
87 * Select mux channel \a ch.
89 void adc_hw_select_ch(uint8_t ch)
91 /* Disable all channels */
92 ADC_CHDR = ADC_CH_MASK;
93 /* Enable select channel */
98 * Start an ADC convertion.
100 uint16_t adc_hw_read(void)
102 ADC_CR = BV(ADC_START);
103 event_wait(&adc_data_ready);
110 void adc_hw_init(void)
112 /* Make sure that interrupt are enabled */
113 IRQ_ASSERT_ENABLED();
115 /* Initialize the dataready event */
116 event_initGeneric(&adc_data_ready);
118 /* Clock ADC peripheral */
119 pmc_periphEnable(ADC_ID);
121 /* Reset adc controller */
122 ADC_CR |= BV(ADC_SWRST);
125 * Set adc mode register:
126 * - Disable hardware trigger and enable software trigger.
127 * - Select normal mode.
131 /* Set ADC_BITS bit convertion resolution. */
133 ADC_MR &= ~BV(ADC_LOWRES);
135 ADC_MR |= BV(ADC_LOWRES);
137 #error No select bit resolution is supported to this CPU
141 LOG_INFO("Computed ADC_CLOCK %ld\n", ADC_CLOCK);
142 ADC_MR |= ((ADC_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
143 LOG_INFO("prescaler[%ld]\n", ADC_PRESCALER);
144 ADC_MR |= ((CONFIG_ADC_SUT << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
145 LOG_INFO("starup[%d]\n", CONFIG_ADC_SUT);
146 ADC_MR |= ((CONFIG_ADC_STTLING << ADC_SETTLING_SHIFT) & ADC_SETTLING_MASK);
147 LOG_INFO("sttime[%d]\n", CONFIG_ADC_STTLING);
148 ADC_MR |= ((CONFIG_ADC_TRACKTIM << ADC_TRACKTIM_SHIFT) & ADC_TRACKTIM_MASK);
149 LOG_INFO("tracking[%d]\n", CONFIG_ADC_TRACKTIM);
150 ADC_MR |= ((CONFIG_ADC_TRANSFER << ADC_TRANSFER_SHIFT) & ADC_TRANSFER_MASK);
151 LOG_INFO("tranfer[%d]\n", CONFIG_ADC_TRANSFER);
153 /* Register and enable irq for adc. */
154 sysirq_setHandler(INT_ADC, adc_conversion_end_irq);
155 ADC_IER = BV(ADC_DRDY);