4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief ADC hardware-specific implementation
35 * This ADC module should be use both whit kernel or none.
36 * If you are using a kernel, the adc drive does not wait the finish of
37 * conversion but use a singal every time a required conversion are
38 * ended. This signal wake up a process that return a result of
39 * conversion. Otherwise, if you not use a kernl, this module wait
40 * whit a loop the finishing of conversion.
43 * \author Daniele Basile <asterix@develer.com>
47 #include "adc_stm32.h"
51 #include "cfg/cfg_adc.h"
52 #include "cfg/cfg_proc.h"
53 #include "cfg/cfg_signal.h"
55 #include <cfg/macros.h>
56 #include <cfg/compiler.h>
57 #include <cfg/debug.h>
59 // Define log settings for cfg/log.h.
60 #define LOG_LEVEL ADC_LOG_LEVEL
61 #define LOG_FORMAT ADC_LOG_FORMAT
65 #include <drv/clock_stm32.h>
66 #include <drv/gpio_stm32.h>
70 struct stm32_adc *adc = (struct stm32_adc *)ADC1_BASE;
73 #include <cfg/module.h>
75 #include <kern/proc.h>
76 #include <kern/signal.h>
78 #include <drv/irq_cm3.h>
81 #if !CONFIG_KERN_SIGNALS
82 #error Signals must be active to use ADC with kernel
85 /* Signal adc convertion end */
86 #define SIG_ADC_COMPLETE SIG_USER0
88 /* ADC waiting process */
89 static struct Process *adc_process;
93 * Simply signal the adc process that convertion is complete.
95 static DECLARE_ISR(adc_conversion_end_irq)
97 sig_post(adc_process, SIG_ADC_COMPLETE);
99 /* Clear the status bit */
100 adc->SR &= ~BV(SR_EOC);
103 static void adc_enable_irq(void)
105 /* Register the IRQ handler */
106 sysirq_setHandler(ADC_IRQHANDLER, adc_conversion_end_irq);
107 adc->CR1 |= BV(CR1_EOCIE);
110 #endif /* CONFIG_KERN */
113 * Select mux channel \a ch.
114 * Generally the stm32 cpu family allow us to program the order
115 * of adc channel that we want to read.
116 * In this driver implementation we put as fist channel to read the
119 void adc_hw_select_ch(uint8_t ch)
121 /* We sample only from one channel */
122 adc->SQR1 |= BV(SQR1_SQ_LEN_SHIFT);
123 adc->SQR3 = (ch & SQR3_SQ_MASK);
127 * Start an ADC convertion.
128 * If a kernel is present, preempt until convertion is complete, otherwise
129 * a busy wait on ADC_DRDY bit is done.
131 uint16_t adc_hw_read(void)
134 /* Ensure ADC is not already in use by another process */
135 ASSERT(adc_process == NULL);
136 adc_process = proc_current();
139 /* Start convertion */
140 adc->CR2 |= CR2_EXTTRIG_SWSTRT_SET;
143 /* Ensure IRQs enabled. */
144 IRQ_ASSERT_ENABLED();
145 sig_wait(SIG_ADC_COMPLETE);
147 /* Prevent race condition in case of preemptive kernel */
148 uint16_t ret = adc->DR;
153 /* Wait in polling until conversion is done */
154 while (!(adc->SR & BV(SR_EOC)));
156 /* Return the last converted data */
164 void adc_hw_init(void)
166 RCC->APB2ENR |= (RCC_APB2_GPIOA | RCC_APB2_GPIOB | RCC_APB2_GPIOC);
167 RCC->APB2ENR |= RCC_APB2_ADC1;
177 adc->CR2 |= BV(CR2_RTSCAL);
178 adc->CR2 |= BV(CR2_CAL);
180 /* Wait in polling until calibration is done */
181 while (adc->CR2 & BV(CR2_CAL));
187 * - Wake up temperature and Vrefint
189 adc->CR2 |= (BV(CR2_ADON) | ADC_EXTERNALTRIGCONV_NONE | BV(CR2_TSVREFE));
191 /* Set 17.1usec sampling time*/
192 adc->SMPR1 |= ((ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH17) |
193 (ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH16) |
194 (ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH15) |
195 (ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH14) |
196 (ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH13) |
197 (ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH12) |
198 (ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH11) |
199 (ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH10));
201 adc->SMPR2 |= ((ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH9) |
202 (ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH8) |
203 (ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH7) |
204 (ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH6) |
205 (ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH5) |
206 (ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH4) |
207 (ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH3) |
208 (ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH2) |
209 (ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH1) |
210 (ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH0));