4 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
5 * This file is part of DevLib - See README.devlib for information.
10 * \author Francesco Sacchi <batt@develer.com>
12 * AT91 advanced interrupt controller.
13 * This file is based on NUT/OS implementation. See license below.
17 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
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20 * modification, are permitted provided that the following conditions
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32 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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45 * For additional information see http://www.ethernut.de/
51 #include <cfg/compiler.h>
56 * Source mode register array.
58 #define AIC_SMR(i) (*((volatile uint32_t *)(AIC_BASE + (i) * 4)))
62 * Priority levels can be between 0 (lowest) and 7 (highest).
64 #define AIC_PRIOR_MASK 0x00000007
67 * Interrupt source type mask.
68 * Internal interrupts can level sensitive or edge triggered.
70 * External interrupts can triggered on positive or negative levels or
71 * on rising or falling edges.
73 #define AIC_SRCTYPE_MASK 0x00000060
75 #define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000 ///< Internal level sensitive.
76 #define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x00000020 ///< Internal edge triggered.
77 #define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00000000 ///< External low level.
78 #define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x00000020 ///< External falling edge.
79 #define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x00000040 ///< External high level.
80 #define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x00000060 ///< External rising edge.
85 * Type for interrupt handlers.
87 typedef void (*irq_handler_t)(void);
89 /** Interrupt Source Vector Registers */
91 /** Source vector register array.
93 * Stores the addresses of the corresponding interrupt handlers.
95 #define AIC_SVR(i) (*((volatile irq_handler_t *)(AIC_BASE + 0x80 + (i) * 4)))
98 /** Interrupt Vector Register */
100 #define AIC_IVR_OFF 0x00000100 ///< IRQ vector register offset.
101 #define AIC_IVR (*((volatile uint32_t *)(AIC_BASE + AIC_IVR_OFF))) ///< IRQ vector register address.
104 /** Fast Interrupt Vector Register */
106 #define AIC_FVR_OFF 0x00000104 ///< FIQ vector register offset.
107 #define AIC_FVR (*((volatile uint32_t *)(AIC_BASE + AIC_FVR_OFF))) ///< FIQ vector register address.
110 /** Interrupt Status Register */
112 #define AIC_ISR_OFF 0x00000108 ///< Interrupt status register offset.
113 #define AIC_ISR (*((volatile uint32_t *)(AIC_BASE + AIC_ISR_OFF))) ///< Interrupt status register address.
114 #define AIC_IRQID_MASK 0x0000001F ///< Current interrupt identifier mask.
117 /** Interrupt Pending Register */
119 #define AIC_IPR_OFF 0x0000010C ///< Interrupt pending register offset.
120 #define AIC_IPR (*((volatile uint32_t *)(AIC_BASE + AIC_IPR_OFF))) ///< Interrupt pending register address.
123 /** Interrupt Mask Register */
125 #define AIC_IMR_OFF 0x00000110 ///< Interrupt mask register offset.
126 #define AIC_IMR (*((volatile uint32_t *)(AIC_BASE + AIC_IMR_OFF))) ///< Interrupt mask register address.
129 /** Interrupt Core Status Register */
131 #define AIC_CISR_OFF 0x00000114 ///< Core interrupt status register offset.
132 #define AIC_CISR (*((volatile uint32_t *)(AIC_BASE + AIC_CISR_OFF))) ///< Core interrupt status register address.
133 #define AIC_NFIQ 1 ///< Core FIQ Status
134 #define AIC_NIRQ 2 ///< Core IRQ Status
137 /** Interrupt Enable Command Register */
139 #define AIC_IECR_OFF 0x00000120 ///< Interrupt enable command register offset.
140 #define AIC_IECR (*((volatile uint32_t *)(AIC_BASE + AIC_IECR_OFF))) ///< Interrupt enable command register address.
143 /** Interrupt Disable Command Register */
145 #define AIC_IDCR_OFF 0x00000124 ///< Interrupt disable command register offset.
146 #define AIC_IDCR (*((volatile uint32_t *)(AIC_BASE + AIC_IDCR_OFF))) ///< Interrupt disable command register address.
149 /** Interrupt Clear Command Register */
151 #define AIC_ICCR_OFF 0x00000128 ///< Interrupt clear command register offset.
152 #define AIC_ICCR (*((volatile uint32_t *)(AIC_BASE + AIC_ICCR_OFF))) ///< Interrupt clear command register address.
155 /** Interrupt Set Command Register */
157 #define AIC_ISCR_OFF 0x0000012C ///< Interrupt set command register offset.
158 #define AIC_ISCR (*((volatile uint32_t *)(AIC_BASE + AIC_ISCR_OFF))) ///< Interrupt set command register address.
161 /** End Of Interrupt Command Register */
163 #define AIC_EOICR_OFF 0x00000130 ///< End of interrupt command register offset.
164 #define AIC_EOICR (*((volatile uint32_t *)(AIC_BASE + AIC_EOICR_OFF))) ///< End of interrupt command register address.
167 /** Spurious Interrupt Vector Register */
169 #define AIC_SPU_OFF 0x00000134 ///< Spurious vector register offset.
170 #define AIC_SPU (*((volatile uint32_t *)(AIC_BASE + AIC_SPU_OFF)== ///< Spurious vector register address.
173 /** Debug Control Register */
175 #define AIC_DCR_OFF 0x0000138 ///< Debug control register offset.
176 #define AIC_DCR (*((volatile uint32_t *)(AIC_BASE + AIC_DCR_OFF))) ///< Debug control register address.
179 /** Fast Forcing Enable Register */
181 #define AIC_FFER_OFF 0x00000140 ///< Fast forcing enable register offset.
182 #define AIC_FFER (*((volatile uint32_t *)(AIC_BASE + AIC_FFER_OFF))) ///< Fast forcing enable register address.
185 /** Fast Forcing Disable Register */
187 #define AIC_FFDR_OFF 0x00000144 ///< Fast forcing disable register address.
188 #define AIC_FFDR (*((volatile uint32_t *)(AIC_BASE + AIC_FFDR_OFF))) ///< Fast forcing disable register address.
191 /** Fast Forcing Status Register */
193 #define AIC_FFSR_OFF 0x00000148 ///< Fast forcing status register address.
194 #define AIC_FFSR (*((volatile uint32_t *)(AIC_BASE + AIC_FFSR_OFF))) ///< Fast forcing status register address.
197 #endif /* AT91_AIC_H */