4 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
5 * This file is part of DevLib - See README.devlib for information.
10 * \author Francesco Sacchi <batt@develer.com>
12 * AT91 periodic interval timer.
13 * This file is based on NUT/OS implementation. See license below.
17 * Copyright (C) 2007 by egnite Software GmbH. All rights reserved.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
23 * 1. Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright
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27 * documentation and/or other materials provided with the distribution.
28 * 3. Neither the name of the copyright holders nor the names of
29 * contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
33 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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45 * For additional information see http://www.ethernut.de/
51 #include <cfg/compiler.h>
53 *Periodic Inverval Timer Mode Register
56 #define PIT_MR_OFF 0x00000000 ///< Mode register offset.
57 #define PIT_MR (*((volatile uint32_t *)(PIT_BASE + PIT_MR_OFF))) ///< Mode register address.
59 #define PIV_MASK 0x000FFFFF ///< Periodic interval value mask.
60 #define PIV_SHIFT 0 ///< Periodic interval value shift.
61 #define PITEN 24 ///< Periodic interval timer enable.
62 #define PITIEN 25 ///< Periodic interval timer interrupt enable.
66 * Periodic Inverval Timer Status Register
69 #define PIT_SR_OFF 0x00000004 ///< Status register offset.
70 #define PIT_SR (*((volatile uint32_t *)(PIT_BASE + PIT_SR_OFF))) ///< Status register address.
72 #define PITS 1 ///< Timer has reached PIV.
76 * Periodic Inverval Timer Value and Image Registers
79 #define PIVR_OFF 0x00000008 ///< Value register offset.
80 #define PIVR (*((volatile uint32_t *)(PIT_BASE + PIVR_OFF))) ///< Value register address.
82 #define PIIR_OFF 0x0000000C ///< Image register offset.
83 #define PIIR (*((volatile uint32_t *)(PIT_BASE + PIIR_OFF))) ///< Image register address.
84 #define CPIV_MASK 0x000FFFFF ///< Current periodic interval value mask.
85 #define CPIV_SHIFT 0 ///< Current periodic interval value SHIFT.
86 #define PICNT_MASK 0xFFF00000 ///< Periodic interval counter mask.
87 #define PICNT_SHIFT 20 ///< Periodic interval counter LSB.
90 #endif /* AT91_PIT_H */