4 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
5 * This file is part of DevLib - See README.devlib for information.
10 * \author Francesco Sacchi <batt@develer.com>
12 * AT91SAM7S register definitions.
13 * This file is based on NUT/OS implementation. See license below.
17 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
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24 * notice, this list of conditions and the following disclaimer.
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32 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
33 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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45 * For additional information see http://www.ethernut.de/
51 #define FLASH_BASE 0x100000UL
52 #define RAM_BASE 0x200000UL
54 #define TC_BASE 0xFFFA0000 ///< Timer/counter base address.
55 #define UDP_BASE 0xFFFB0000 ///< USB device port base address.
56 #define TWI_BASE 0xFFFB8000 ///< Two-wire interface base address.
57 #define USART0_BASE 0xFFFC0000 ///< USART 0 base address.
58 #define USART1_BASE 0xFFFC4000 ///< USART 1 base address.
59 #define PWMC_BASE 0xFFFCC000 ///< PWM controller base address.
60 #define SSC_BASE 0xFFFD4000 ///< Serial synchronous controller base address.
61 #define ADC_BASE 0xFFFD8000 ///< ADC base address.
62 #define SPI_BASE 0xFFFE0000 ///< SPI0 base address.
64 #define AIC_BASE 0xFFFFF000 ///< AIC base address.
65 #define DBGU_BASE 0xFFFFF200 ///< DBGU base address.
66 #define PIOA_BASE 0xFFFFF400 ///< PIO A base address.
67 #define PMC_BASE 0xFFFFFC00 ///< PMC base address.
68 #define RSTC_BASE 0xFFFFFD00 ///< Resect controller register base address.
69 #define RTT_BASE 0xFFFFFD20 ///< Realtime timer base address.
70 #define PIT_BASE 0xFFFFFD30 ///< Periodic interval timer base address.
71 #define WDT_BASE 0xFFFFFD40 ///< Watch Dog register base address.
72 #define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address.
73 #define MC_BASE 0xFFFFFF00 ///< Memory controller base.
77 //TODO: add other peripherals
79 /** Peripheral Identifiers and Interrupts */
81 #define FIQ_ID 0 ///< Fast interrupt ID.
82 #define SYSC_ID 1 ///< System controller interrupt.
83 #define PIOA_ID 2 ///< Parallel I/O controller ID.
84 /* ID 3 is reserved */
85 #define ADC_ID 4 ///< Analog to digital converter ID.
86 #define SPI_ID 5 ///< Serial peripheral interface ID.
87 #define US0_ID 6 ///< USART 0 ID.
88 #define US1_ID 7 ///< USART 1 ID.
89 #define SSC_ID 8 ///< Synchronous serial controller ID.
90 #define TWI_ID 9 ///< Two-wire interface ID.
91 #define PWMC_ID 10 ///< PWM controller ID.
92 #define UDP_ID 11 ///< USB device port ID.
93 #define TC0_ID 12 ///< Timer 0 ID.
94 #define TC1_ID 13 ///< Timer 1 ID.
95 #define TC2_ID 14 ///< Timer 2 ID.
97 #define IRQ0_ID 30 ///< External interrupt 0 ID.
98 #define IRQ1_ID 31 ///< External interrupt 1 ID.
101 #warning Revise me after this line!
103 #define PERIPH_RPR_OFF 0x00000100 ///< Receive pointer register offset.
104 #define PERIPH_RCR_OFF 0x00000104 ///< Receive counter register offset.
105 #define PERIPH_TPR_OFF 0x00000108 ///< Transmit pointer register offset.
106 #define PERIPH_TCR_OFF 0x0000010C ///< Transmit counter register offset.
107 #define PERIPH_RNPR_OFF 0x00000110 ///< Receive next pointer register offset.
108 #define PERIPH_RNCR_OFF 0x00000114 ///< Receive next counter register offset.
109 #define PERIPH_TNPR_OFF 0x00000118 ///< Transmit next pointer register offset.
110 #define PERIPH_TNCR_OFF 0x0000011C ///< Transmit next counter register offset.
111 #define PERIPH_PTCR_OFF 0x00000120 ///< PDC transfer control register offset.
112 #define PERIPH_PTSR_OFF 0x00000124 ///< PDC transfer status register offset.
114 #define PDC_RXTEN 0x00000001 ///< Receiver transfer enable.
115 #define PDC_RXTDIS 0x00000002 ///< Receiver transfer disable.
116 #define PDC_TXTEN 0x00000100 ///< Transmitter transfer enable.
117 #define PDC_TXTDIS 0x00000200 ///< Transmitter transfer disable.
122 #define USART_HAS_PDC
124 #define PIO_HAS_MULTIDRIVER
125 #define PIO_HAS_PULLUP
126 #define PIO_HAS_PERIPHERALSELECT
127 #define PIO_HAS_OUTPUTWRITEENABLE
130 /** Historical SPI0 Peripheral Multiplexing Names */
132 #define SPI0_NPCS0_PA12A 12 ///< Port bit number on PIO-A Perpheral A.
133 #define SPI0_NPCS1_PA13A 13 ///< Port bit number on PIO-A Perpheral A.
134 #define SPI0_NPCS1_PA07B 7 ///< Port bit number on PIO-A Perpheral B.
135 #define SPI0_NPCS1_PB13B 13 ///< Port bit number on PIO-B Perpheral B.
136 #define SPI0_NPCS2_PA14A 14 ///< Port bit number on PIO-A Perpheral A.
137 #define SPI0_NPCS2_PA08B 8 ///< Port bit number on PIO-A Perpheral B.
138 #define SPI0_NPCS2_PB14B 14 ///< Port bit number on PIO-B Perpheral B.
139 #define SPI0_NPCS3_PA15A 15 ///< Port bit number on PIO-A Perpheral A.
140 #define SPI0_NPCS3_PA09B 9 ///< Port bit number on PIO-A Perpheral B.
141 #define SPI0_NPCS3_PB17B 17 ///< Port bit number on PIO-B Perpheral B.
142 #define SPI0_MISO_PA16A 16 ///< Port bit number on PIO-A Perpheral A.
143 #define SPI0_MOSI_PA17A 17 ///< Port bit number on PIO-A Perpheral A.
144 #define SPI0_SPCK_PA18A 18 ///< Port bit number on PIO-A Perpheral A.
147 /** USART Peripheral Multiplexing */
160 #define PB23_DCD1_B 23
161 #define PB24_DSR1_B 24
162 #define PB25_DTR1_B 25
163 #define PB26_RI1_B 26
166 /** SPI Peripheral Multiplexing */
168 #define PA16_SPI0_MISO_A 16
169 #define PA17_SPI0_MOSI_A 17
170 #define PA18_SPI0_SPCK_A 18
171 #define PA12_SPI0_NPCS0_A 12
172 #define PA13_SPI0_NPCS1_A 13
173 #define PA7_SPI0_NPCS1_B 7
174 #define PA14_SPI0_NPCS2_A 14
175 #define PB14_SPI0_NPCS2_B 14
176 #define PA8_SPI0_NPCS2_B 8
177 #define PA15_SPI0_NPCS3_A 15
178 #define PA9_SPI0_NPCS3_B 9
180 #define SPI0_PINS _BV(PA16_SPI0_MISO_A) | _BV(PA17_SPI0_MOSI_A) | _BV(PA18_SPI0_SPCK_A)
181 #define SPI0_PIO_BASE PIOA_BASE
182 #define SPI0_PSR_OFF PIO_ASR_OFF
184 #define SPI0_CS0_PIN _BV(PA12_SPI0_NPCS0_A)
185 #define SPI0_CS0_PIO_BASE PIOA_BASE
186 #define SPI0_CS0_PSR_OFF PIO_ASR_OFF
189 #define SPI0_CS1_PIN _BV(PA13_SPI0_NPCS1_A)
190 #define SPI0_CS1_PIO_BASE PIOA_BASE
191 #define SPI0_CS1_PSR_OFF PIO_ASR_OFF
195 #define SPI0_CS2_PIN _BV(PA14_SPI0_NPCS2_A)
196 #define SPI0_CS2_PIO_BASE PIOA_BASE
197 #define SPI0_CS2_PSR_OFF PIO_ASR_OFF
201 #define SPI0_CS3_PIN _BV(PA15_SPI0_NPCS3_A)
202 #define SPI0_CS3_PIO_BASE PIOA_BASE
203 #define SPI0_CS3_PSR_OFF PIO_ASR_OFF
206 #define PA24_SPI1_MISO_B 24
207 #define PA23_SPI1_MOSI_B 23
208 #define PA22_SPI1_SPCK_B 22
209 #define PA21_SPI1_NPCS0_B 21
210 #define PA25_SPI1_NPCS1_B 25
211 #define PB13_SPI0_NPCS1_B 13
212 #define PA2_SPI1_NPCS1_B 2
213 #define PB10_SPI1_NPCS1_B 10
214 #define PA26_SPI1_NPCS2_B 26
215 #define PA3_SPI1_NPCS2_B 3
216 #define PB11_SPI1_NPCS2_B 11
217 #define PB17_SPI0_NPCS3_B 17
218 #define PA4_SPI1_NPCS3_B 4
219 #define PA29_SPI1_NPCS3_B 29
220 #define PB16_SPI1_NPCS3_B 16
222 #define SPI1_PINS _BV(PA24_SPI1_MISO_B) | _BV(PA23_SPI1_MOSI_B) | _BV(PA22_SPI1_SPCK_B)
223 #define SPI1_PIO_BASE PIOA_BASE
224 #define SPI1_PSR_OFF PIO_BSR_OFF
226 #define SPI1_CS0_PIN _BV(PA21_SPI1_NPCS0_B)
227 #define SPI1_CS0_PIO_BASE PIOA_BASE
228 #define SPI1_CS0_PSR_OFF PIO_BSR_OFF
231 #define SPI1_CS1_PIN _BV(PA25_SPI1_NPCS1_B)
232 #define SPI1_CS1_PIO_BASE PIOA_BASE
233 #define SPI1_CS1_PSR_OFF PIO_BSR_OFF
237 #define SPI1_CS2_PIN _BV(PA26_SPI1_NPCS2_B)
238 #define SPI1_CS2_PIO_BASE PIOA_BASE
239 #define SPI1_CS2_PSR_OFF PIO_BSR_OFF
243 #define SPI1_CS3_PIN _BV(PA29_SPI1_NPCS3_B)
244 #define SPI1_CS3_PIO_BASE PIOA_BASE
245 #define SPI1_CS3_PSR_OFF PIO_BSR_OFF
250 /** EMAC Interface Peripheral Multiplexing */
252 #define PB0_ETXCK_EREFCK_A 0
253 #define PB1_ETXEN_A 1
259 #define PB7_ERXER_A 7
261 #define PB9_EMDIO_A 9
262 #define PB10_ETX2_A 10
263 #define PB11_ETX3_A 11
264 #define PB12_ETXER_A 12
265 #define PB13_ERX2_A 13
266 #define PB14_ERX3_A 14
267 #define PB15_ERXDV_ECRSDV_A 15
268 #define PB16_ECOL_A 16
269 #define PB17_ERXCK_A 17
270 #define PB18_EF100_A 18
273 /** Debug Unit Peripheral Multiplexing */
275 #define PA27_DRXD_A 27
276 #define PA28_DTXD_A 28
279 /** Synchronous Serial Controller Peripheral Multiplexing */
281 #define PA23_TD_A 23 ///< Transmit data pin.
282 #define PA24_RD_A 24 ///< Receive data pin.
283 #define PA22_TK_A 22 ///< Transmit clock pin.
284 #define PA25_RK_A 25 ///< Receive clock pin.
285 #define PA21_TF_A 21 ///< Transmit frame sync. pin.
286 #define PA26_RF_A 26 ///< Receive frame sync. pin.
289 /** Two Wire Interface Peripheral Multiplexing */
291 #define PA10_TWD_A 10 ///< Two wire serial data pin.
292 #define PA11_TWCK_A 11 ///< Two wire serial clock pin.
295 /** Timer/Counter Peripheral Multiplexing */
297 #define PB23_TIOA0_A 23
298 #define PB24_TIOB0_A 24
299 #define PB12_TCLK0_B 12
301 #define PB25_TIOA1_A 25
302 #define PB26_TIOB1_A 26
303 #define PB19_TCLK1_B 19
305 #define PB27_TIOA2_A 27
306 #define PB28_TIOB2_A 28
307 #define PA15_TCLK2_B 15
310 /** Clocks, Oscillators and PLLs Peripheral Multiplexing */
313 #define PB20_PCK0_B 20
314 #define PA13_PCK1_B 13
315 #define PB29_PCK1_A 29
316 #define PB21_PCK1_B 21
317 #define PA30_PCK2_B 30
318 #define PB30_PCK2_A 30
319 #define PB22_PCK2_B 22
320 #define PA27_PCK3_B 27
323 /** Advanced Interrupt Controller Peripheral Multiplexing */
325 #define PA29_FIQ_A 29
326 #define PA30_IRQ0_A 30
327 #define PA14_IRQ1_B 14
330 /** ADC Interface Peripheral Multiplexing */
332 #define PB18_ADTRG_B 18 ///< ADC trigger pin.
335 /** CAN Interface Peripheral Multiplexing */
337 #define PA19_CANRX_A 19
338 #define PA20_CANTX_A 20
341 /** PWM Peripheral Multiplexing */
343 #define PB19_PWM0_A 19
344 #define PB27_PWM0_B 27
345 #define PB20_PWM1_A 20
346 #define PB28_PWM1_B 28
347 #define PB21_PWM2_A 21
348 #define PB29_PWM2_B 29
349 #define PB22_PWM3_A 22
350 #define PB30_PWM3_B 30
353 #endif /* AT91SAM7S_H */