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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 Clocking driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include "clock_lm3s.h"
40 #include <cfg/compiler.h>
41 #include <cfg/debug.h>
46 /* The PLL VCO frequency is 400 MHz */
47 #define PLL_VCO 400000000UL
49 /* Extract the system clock divisor from the RCC register */
50 #define RCC_TO_DIV(rcc) \
51 (((rcc & SYSCTL_RCC_SYSDIV_MASK) >> \
52 SYSCTL_RCC_SYSDIV_SHIFT) + 1)
55 * Very small delay: each loop takes 3 cycles.
57 void NAKED lm3s_busyWait(unsigned long iterations)
59 register uint32_t __n asm("r0") = iterations;
65 : : "r"(__n) : "memory", "cc");
68 INLINE unsigned long clock_get_rate(void)
70 reg32_t rcc = HWREG(SYSCTL_RCC);
72 return rcc & SYSCTL_RCC_USESYSDIV ?
73 PLL_VCO / 2 / RCC_TO_DIV(rcc) : PLL_VCO;
77 * Try to evaluate the correct SYSDIV value depending on the desired CPU
80 INLINE int evaluate_sysdiv(unsigned long freq)
85 * NOTE: with BYPASS=0, SYSDIV < 3 are reserved values (see LM3S1968
86 * Microcontroller DATASHEET, p.78).
88 for (i = 3; i < 16; i++)
89 if (freq >= (PLL_VCO / 2 / (i + 1)))
101 * PLL may not function properly at default LDO setting.
105 * In designs that enable and use the PLL module, unstable device
106 * behavior may occur with the LDO set at its default of 2.5 volts or
107 * below (minimum of 2.25 volts). Designs that do not use the PLL
108 * module are not affected.
110 * Workaround: Prior to enabling the PLL module, it is recommended that
111 * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using
112 * the LDO Power Control (LDOPCTL) register.
114 * Silicon Revision Affected: A1, A2
116 * See also: Stellaris LM3S1968 A2 Errata documentation.
118 if (REVISION_IS_A1 | REVISION_IS_A2)
119 HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V;
121 rcc = HWREG(SYSCTL_RCC);
122 rcc2 = HWREG(SYSCTL_RCC2);
125 * Step #1: bypass the PLL and system clock divider by setting the
126 * BYPASS bit and clearing the USESYS bit in the RCC register. This
127 * configures the system to run off a “raw” clock source (using the
128 * main oscillator or internal oscillator) and allows for the new PLL
129 * configuration to be validated before switching the system clock to
132 rcc |= SYSCTL_RCC_BYPASS;
133 rcc &= ~SYSCTL_RCC_USESYSDIV;
134 rcc2 |= SYSCTL_RCC2_BYPASS2;
136 /* Write back RCC/RCC2 registers */
137 HWREG(SYSCTL_RCC) = rcc;
138 HWREG(SYSCTL_RCC) = rcc2;
143 * Step #2: select the crystal value (XTAL) and oscillator source
144 * (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL
145 * field automatically pulls valid PLL configuration data for the
146 * appropriate crystal, and clearing the PWRDN bit powers and enables
147 * the PLL and its output.
150 /* Enable the main oscillator first. */
151 rcc &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
152 rcc |= SYSCTL_RCC_IOSCDIS;
154 /* Do not override RCC register fields */
155 rcc2 &= ~SYSCTL_RCC2_USERCC2;
157 rcc &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_PWRDN);
158 rcc |= XTAL_FREQ | SYSCTL_RCC_OSCSRC_MAIN;
160 /* Clear the PLL lock interrupt. */
161 HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;
163 HWREG(SYSCTL_RCC) = rcc;
164 HWREG(SYSCTL_RCC) = rcc2;
169 * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
170 * set the USESYS bit in RCC. The SYSDIV field determines the system
171 * frequency for the microcontroller.
173 rcc &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV);
176 for (i = 3; i < 16; i++)
177 if (CPU_FREQ >= (clk / (i + 1)))
179 rcc |= SYSCTL_RCC_USESYSDIV |
180 (evaluate_sysdiv(CPU_FREQ) << SYSCTL_RCC_SYSDIV_SHIFT);
183 * Step #4: wait for the PLL to lock by polling the PLLLRIS bit in the
184 * Raw Interrupt Status (RIS) register.
186 for (i = 0; i < 32768; i++)
187 if (HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)
191 * Step #5: enable use of the PLL by clearing the BYPASS bit in
194 rcc &= ~SYSCTL_RCC_BYPASS;
196 HWREG(SYSCTL_RCC) = rcc;