4 * This file is part of BeRTOS.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief ATSAM3 clock setup.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "clock_sam3.h"
39 #include <io/sam3_pmc.h>
40 #include <io/sam3_sysctl.h>
41 #include <cfg/compiler.h>
42 #include <cfg/macros.h>
45 /* Frequency of board main oscillator */
46 #define BOARDOSC_FREQ 12000000
48 /* Main crystal oscillator startup time, optimal value for CPU_FREQ == 48 MHz */
49 #define BOARD_OSC_COUNT (CKGR_MOR_MOSCXTST(0x8))
51 /* Timer countdown timeout for clock initialization operations */
52 #define CLOCK_TIMEOUT 0xFFFFFFFF
56 * Try to evaluate the correct divider and multiplier value depending
57 * on the desired CPU frequency.
59 * We try all combinations in a certain range of divider and multiplier
60 * values. The range can change, with better match with "strange"
61 * frequencies, but boot time will be longer.
63 * Limits for SAM3N: divider [1,255], multiplier [1,2047].
65 INLINE uint32_t evaluate_pll(void)
67 int mul, div, best_mul, best_div;
68 int best_delta = CPU_FREQ;
71 for (mul = 1; mul <= 8; mul++)
73 for (div = 1; div <= 24; div++)
75 freq = BOARDOSC_FREQ / div * (1 + mul);
76 if (ABS((int)CPU_FREQ - freq) < best_delta) {
77 best_delta = ABS((int)CPU_FREQ - freq);
84 // Bit 29 must always be set to 1
85 return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul) | BV(29);
93 // Select external slow clock
94 if (!(SUPC_SR_R & SUPC_SR_OSCSEL))
96 SUPC_CR_R = SUPC_CR_XTALSEL | SUPC_CR_KEY(0xA5);
97 while (!(SUPC_SR_R & SUPC_SR_OSCSEL));
100 // Initialize main oscillator
101 if (!(CKGR_MOR_R & CKGR_MOR_MOSCSEL))
103 CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
104 timeout = CLOCK_TIMEOUT;
105 while (!(PMC_SR_R & PMC_SR_MOSCXTS) && --timeout);
108 // Switch to external oscillator
109 CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
110 timeout = CLOCK_TIMEOUT;
111 while (!(PMC_SR_R & PMC_SR_MOSCSELS) && --timeout);
113 PMC_MCKR_R = (PMC_MCKR_R & ~(uint32_t)PMC_MCKR_CSS_M) | PMC_MCKR_CSS_MAIN_CLK;
114 timeout = CLOCK_TIMEOUT;
115 while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
117 // Initialize and enable PLL clock
118 CKGR_PLLR_R = evaluate_pll() | CKGR_PLLR_STUCKTO1 | CKGR_PLLR_PLLCOUNT(0x1);
119 timeout = CLOCK_TIMEOUT;
120 while (!(PMC_SR_R & PMC_SR_LOCK) && --timeout);
122 PMC_MCKR_R = PMC_MCKR_CSS_MAIN_CLK;
123 timeout = CLOCK_TIMEOUT;
124 while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
126 PMC_MCKR_R = PMC_MCKR_CSS_PLL_CLK;
127 timeout = CLOCK_TIMEOUT;
128 while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);