4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Atmel SAM3 clock setup.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "clock_sam3.h"
39 #include <cfg/compiler.h>
40 #include <cfg/macros.h>
44 /* Frequency of board main oscillator */
45 #define BOARDOSC_FREQ 12000000
47 /* Timer countdown timeout for clock initialization operations */
48 #define CLOCK_TIMEOUT 0xFFFFFFFF
51 #if CPU_FREQ == 84000000 || CPU_FREQ == 48000000
53 INLINE uint32_t evaluate_pll(void)
55 return CKGR_PLLR_MUL(CPU_FREQ / BOARDOSC_FREQ * 2 - 1) | CKGR_PLLR_DIV(2);
60 #warning CPU clock frequency non-standard setting: multiplier and divider values \
61 will be computed at runtime: effective computed frequency could be different \
65 * Try to evaluate the correct divider and multiplier value depending
66 * on the desired CPU frequency.
68 * We try all combinations in a certain range of divider and multiplier
69 * values. Start with higher multipliers and divisors, generally better.
71 INLINE uint32_t evaluate_pll(void)
73 int mul, div, best_mul, best_div;
74 int best_delta = CPU_FREQ;
77 for (mul = 13; mul > 0; mul--)
79 for (div = 24; div > 0; div--)
81 freq = BOARDOSC_FREQ / div * (1 + mul);
82 if (ABS((int)CPU_FREQ - freq) < best_delta) {
83 best_delta = ABS((int)CPU_FREQ - freq);
90 return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul);
99 /* Disable watchdog */
100 WDT_MR = BV(WDT_WDDIS);
102 /* Set wait states for flash access, needed for higher CPU clock rates */
103 EEFC0_FMR = EEFC_FMR_FWS(3);
105 EEFC1_FMR = EEFC_FMR_FWS(3);
108 // Initialize main oscillator
109 if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL)))
111 CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8)
112 | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN);
113 timeout = CLOCK_TIMEOUT;
114 while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
117 // Switch to external oscillator
118 CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8)
119 | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL);
120 timeout = CLOCK_TIMEOUT;
121 while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
123 // Initialize and enable PLL clock
124 CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x2);
125 timeout = CLOCK_TIMEOUT;
126 while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout);
128 PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
129 timeout = CLOCK_TIMEOUT;
130 while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
132 PMC_MCKR = PMC_MCKR_CSS_PLL_CLK;
133 timeout = CLOCK_TIMEOUT;
134 while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
136 /* Enable clock on PIO for inputs */
137 // TODO: move this in gpio_init() for better power management?
138 pmc_periphEnable(PIOA_ID);
139 pmc_periphEnable(PIOB_ID);
140 pmc_periphEnable(PIOC_ID);
142 pmc_periphEnable(PIOD_ID);
143 pmc_periphEnable(PIOE_ID);
144 pmc_periphEnable(PIOF_ID);