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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32 Clocking driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include "clock_stm32.h"
40 #include <cfg/compiler.h>
41 #include <cfg/debug.h>
47 INLINE int rcc_get_flag_status(uint32_t flag)
52 /* Get the RCC register index */
54 /* The flag to check is in CR register */
57 /* The flag to check is in BDCR register */
60 /* The flag to check is in CSR register */
63 /* Get the flag position */
64 id = flag & FLAG_MASK;
66 return reg & (1 << id);
69 INLINE uint16_t pll_clock(void)
71 unsigned int div, mul;
73 /* Hopefully this is evaluate at compile time... */
74 for (div = 2; div; div--)
75 for (mul = 2; mul <= 16; mul++)
76 if (CPU_FREQ <= (PLL_VCO / div * mul))
78 return mul << 8 | div;
81 INLINE void rcc_pll_config(void)
83 reg32_t reg = RCC->CFGR & CFGR_PLL_MASK;
85 /* Evaluate clock parameters */
86 uint16_t clock = pll_clock();
87 uint32_t pll_mul = ((clock >> 8) - 2) << 18;
88 uint32_t pll_div = ((clock & 0xff) << 1 | 1) << 16;
90 /* Set the PLL configuration bits */
91 reg |= pll_div | pll_mul;
93 /* Store the new value */
100 INLINE void rcc_set_clock_source(uint32_t source)
104 reg = RCC->CFGR & CFGR_SW_MASK;
109 void clock_init(void)
111 /* Initialize global RCC structure */
112 RCC = (struct RCC *)RCC_BASE;
114 /* Enable the internal oscillator */
116 while (!rcc_get_flag_status(RCC_FLAG_HSIRDY));
118 /* Clock the system from internal HSI RC (8 MHz) */
119 rcc_set_clock_source(RCC_SYSCLK_HSI);
121 /* Enable external oscillator */
122 RCC->CR &= CR_HSEON_RESET;
123 RCC->CR &= CR_HSEBYP_RESET;
124 RCC->CR |= CR_HSEON_SET;
125 while (!rcc_get_flag_status(RCC_FLAG_HSERDY));
127 /* Initialize PLL according to CPU_FREQ */
129 while(!rcc_get_flag_status(RCC_FLAG_PLLRDY));
131 /* Configure USB clock (48MHz) */
132 *CFGR_USBPRE_BB = RCC_USBCLK_PLLCLK_1DIV5;
133 /* Configure ADC clock: PCLK2 (9MHz) */
134 RCC->CFGR &= CFGR_ADCPRE_RESET_MASK;
135 RCC->CFGR |= RCC_PCLK2_DIV8;
136 /* Configure system clock dividers: PCLK2 (72MHz) */
137 RCC->CFGR &= CFGR_PPRE2_RESET_MASK;
138 RCC->CFGR |= RCC_HCLK_DIV1 << 3;
139 /* Configure system clock dividers: PCLK1 (36MHz) */
140 RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
141 RCC->CFGR |= RCC_HCLK_DIV2;
142 /* Configure system clock dividers: HCLK */
143 RCC->CFGR &= CFGR_HPRE_RESET_MASK;
144 RCC->CFGR |= RCC_SYSCLK_DIV1;
146 /* Set 1 wait state for the flash memory */
147 *(reg32_t *)FLASH_BASE = 0x12;
149 /* Clock the system from the PLL */
150 rcc_set_clock_source(RCC_SYSCLK_PLLCLK);