4 * This file is part of BeRTOS.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief DAC hardware-specific implementation
35 * \author Daniele Basile <asterix@develer.com>
40 #include "cfg/cfg_dac.h"
42 #include <cfg/macros.h>
43 #include <cfg/compiler.h>
45 // Define log settings for cfg/log.h.
46 #define LOG_LEVEL DAC_LOG_LEVEL
47 #define LOG_FORMAT DAC_LOG_FORMAT
51 #include <drv/irq_cm3.h>
53 #include <cpu/types.h>
66 struct DacHardware dac_hw;
68 #if CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH0 /* Select Timer counter TIO Channel 0 */
69 #define DAC_TC_ID TC0_ID
70 #define DAC_TC_CCR TC0_CCR0
71 #define DAC_TC_IDR TC0_IDR0
72 #define DAC_TC_CMR TC0_CMR0
73 #define DAC_TC_SR TC0_SR0
74 #define DAC_TC_RA TC0_RA0
75 #define DAC_TC_RC TC0_RC0
76 #elif CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH1 /* Select Timer counter TIO Channel 1 */
77 #define DAC_TC_ID TC1_ID
78 #define DAC_TC_CCR TC0_CCR1
79 #define DAC_TC_IDR TC0_IDR1
80 #define DAC_TC_CMR TC0_CMR1
81 #define DAC_TC_SR TC0_SR1
82 #define DAC_TC_RA TC0_RA1
83 #define DAC_TC_RC TC0_RC1
84 #elif CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH2 /* Select Timer counter TIO Channel 2 */
85 #define DAC_TC_ID TC2_ID
86 #define DAC_TC_CCR TC0_CCR2
87 #define DAC_TC_IDR TC0_IDR2
88 #define DAC_TC_CMR TC0_CMR2
89 #define DAC_TC_SR TC0_SR2
90 #define DAC_TC_RA TC0_RA2
91 #define DAC_TC_RC TC0_RC2
92 #elif CONFIG_DAC_TIMER == DACC_TRGSEL_PWM0 || CONFIG_DAC_TIMER == DACC_TRGSEL_PWM1
93 #error unimplemented pwm triger select.
96 INLINE void tc_setup(uint32_t freq, size_t n_sample)
98 pmc_periphEnable(DAC_TC_ID);
100 /* Disable TC clock */
101 DAC_TC_CCR = TC_CCR_CLKDIS;
102 /* Disable interrupts */
103 DAC_TC_IDR = 0xFFFFFFFF;
104 /* Clear status register */
105 volatile uint32_t dummy = DAC_TC_SR;
109 * Setup the timer counter:
110 * - select clock TCLK1 (MCK/2)
111 * - enable wave form mode
112 * - RA compare effect SET
113 * - RC compare effect CLEAR
114 * - UP mode with automatic trigger on RC Compare
116 DAC_TC_CMR = TC_TIMER_CLOCK1 | BV(TC_CMR_WAVE) | TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR | BV(TC_CMR_CPCTRG);
119 * Compute the sample frequency
120 * the RC counter will update every MCK/2 (see above)
121 * so to convert one sample at the user freq we generate
122 * the trigger every TC_CLK / (numer_of_sample * user_freq)
123 * where TC_CLK = MCK / 2.
125 uint32_t rc = DIV_ROUND((CPU_FREQ / 2), n_sample * freq);
127 /* generate the square wave with duty = 50% */
128 DAC_TC_RA = DIV_ROUND(50 * rc, 100);
131 PIO_PERIPH_SEL(PIOB_BASE, BV(25), PIO_PERIPH_B);
134 INLINE void tc_start(void)
136 DAC_TC_CCR = BV(TC_CCR_CLKEN)| BV(TC_CCR_SWTRG);
139 INLINE void tc_stop(void)
141 DAC_TC_CCR = BV(TC_CCR_CLKDIS);
144 static int sam3x_dac_write(struct Dac *dac, unsigned channel, uint16_t sample)
148 ASSERT(channel <= DAC_MAXCH);
150 DACC_MR |= (channel << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
151 DACC_CHER |= BV(channel);
158 static void sam3x_dac_setCh(struct Dac *dac, uint32_t mask)
160 /* we have only the ch0 and ch1 */
161 ASSERT(mask < BV(3));
162 dac->hw->channels = mask;
165 static void sam3x_dac_setSampleRate(struct Dac *dac, uint32_t rate)
169 /* Eneble hw trigger */
170 DACC_MR |= BV(DACC_TRGEN) | (CONFIG_DAC_TIMER << DACC_TRGSEL_SHIFT);
171 dac->hw->rate = rate;
174 static void sam3x_dac_conversion(struct Dac *dac, void *buf, size_t len)
176 if (dac->hw->channels & BV(DACC_CH0))
177 DACC_MR |= (DACC_CH0 << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
179 if (dac->hw->channels & BV(DACC_CH1))
180 DACC_MR |= (DACC_CH1 << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
182 DACC_CHER |= dac->hw->channels;
184 /* setup timer and start it */
185 tc_setup(dac->hw->rate, len);
188 /* Setup dma and start it */
189 DACC_TPR = (uint32_t)buf ;
191 DACC_PTCR |= BV(DACC_PTCR_TXTEN);
194 static bool sam3x_dac_isFinished(struct Dac *dac)
200 static void sam3x_dac_start(struct Dac *dac, void *buf, size_t len, size_t slice_len)
208 static void sam3x_dac_stop(struct Dac *dac)
214 void dac_init(struct Dac *dac)
217 /* Fill the virtual table */
218 dac->ctx.write = sam3x_dac_write;
219 dac->ctx.setCh = sam3x_dac_setCh;
220 dac->ctx.setSampleRate = sam3x_dac_setSampleRate;
221 dac->ctx.conversion = sam3x_dac_conversion;
222 dac->ctx.isFinished = sam3x_dac_isFinished;
223 dac->ctx.start = sam3x_dac_start;
224 dac->ctx.stop = sam3x_dac_stop;
225 DB(dac->ctx._type = DAC_SAM3X;)
228 /* Clock DAC peripheral */
229 pmc_periphEnable(DACC_ID);
232 DACC_CR |= BV(DACC_SWRST);
235 /* Configure the dac */
236 DACC_MR |= (CONFIG_DAC_REFRESH << DACC_REFRESH_SHIFT) & DACC_REFRESH_MASK;
237 DACC_MR |= (CONFIG_DAC_STARTUP << DACC_STARTUP_SHIFT) & DACC_STARTUP_MASK;