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29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
33 * \brief Function library for AT45DB081D Flash memory.
36 * \version $Id: dflash.h 15402 2007-04-10 09:10:56Z asterix $
37 * \author Daniele Basile <asterix@develer.com>
41 #ifndef DRV_DATAFLASH_H
42 #define DRV_DATAFLASH_H
44 #include <kern/kfile.h>
45 #include <cfg/compiler.h>
49 #include <appconfig.h>
51 #warning This driver must be test before use!
54 * Type definition for dflash memory.
56 typedef uint32_t dataflashAddr_t;
57 typedef uint32_t dataflashOffset_t;
58 typedef uint32_t dataflashSize_t;
60 #define RESET_PULSE_WIDTH 10 // Width of reset pulse in usec.
61 #define BUSY_BIT 0x80 // Select a busy bit in status register.
62 #define CMP_BIT 0x40 // Select a compare bit in status register.
65 * Select 2,3,4,5 bits of status register, those
66 * bits indicate a id of density device (see datasheet for
69 #define GET_ID_DESITY_DEVICE(reg_stat)\
78 * \note RESET and WP are asserted when logic
82 #define RESET PC0 ///< Connect to RESET pin of flash memory
83 #define WP PC1 ///< Connect to WP pin of flash memory
84 #define DATAFLASH_PORT PORTC ///< Micro pin PORT register.
85 #define DATAFLASH_PIN PINC ///< Micro pin PIN register.
86 #define DATAFLASH_DDR DDRC ///< Micro pin DDR register.
94 #define RESET_LOW() do { DATAFLASHs_PORT &= ~BV(RESET); } while(0)
95 #define RESET_HIGH() do { DATAFLASH_PORT |= BV(RESET); } while(0)
96 #define WP_LOW() do { DATAFLASH_PORT &= ~BV(WP); } while(0)
97 #define WP_HIGH() do { DATAFLASH_PORT |= BV(WP); } while(0)
103 * \note To reset flash memory it needs a pulse
104 * long about 10 usec. To do this we insert a
109 #define RESET_OUT() do { DATAFLASH_DDR |= BV(RESET); } while(0)
110 #define WP_OUT() do { DATAFLASH_DDR |= BV(WP); } while(0)
111 #define WRITE_ENABLE() WP_HIGH()
112 #define WRITE_DISABLE() WP_LOW()
113 #define RESET_ENABLE() RESET_LOW()
114 #define RESET_DISABLE() RESET_HIGH()
121 * \note Below are defined valid flash memory support to
122 * this drive. Every time we call dataflash_init() function we check
123 * if memory defined are right (see dataflash.c form more detail).
126 #define DATAFLASH_AT45DB041B 1
127 #define DATAFLASH_AT45DB081D 2
128 #define DATAFLASH_AT45DB161D 3
130 #if CONFIG_DATA_FLASH == DATAFLASH_AT45DB161D
131 #define DATAFLASH_ID_DEVICE_DENSITY 0xb ///< This indicate AT45DB161D data flah memory.
132 #define DATAFLASH_PAGE_SIZE 528 ///< Number of byte in one page.
133 #define DATAFLASH_PAGE_ADDRESS_BIT 10 ///< Number bit for addressing one page.
134 #define DATAFLASH_NUM_PAGE 4096 ///< Number page in data flash memory.
135 #elif CONFIG_DATA_FLASH == DATAFLASH_AT45DB081D
136 #define DATAFLASH_ID_DEVICE_DENSITY 0x9 ///< This indicate AT45DB081D data flah memory.
137 #define DATAFLASH_PAGE_SIZE 264 ///< Number of byte in one page.
138 #define DATAFLASH_PAGE_ADDRESS_BIT 9 ///< Number bit for addressing one page.
139 #define DATAFLASH_NUM_PAGE 4096 ///< Number page in data flash memory.
140 #elif CONFIG_DATA_FLASH == DATAFLASH_AT45DB041B
141 #define DATAFLASH_ID_DEVICE_DENSITY 0x7 ///< This indicate AT45DB041B data flah memory.
142 #define DATAFLASH_PAGE_SIZE 264 ///< Number of byte in one page.
143 #define DATAFLASH_PAGE_ADDRESS_BIT 9 ///< Number bit for addressing one page.
144 #define DATAFLASH_NUM_PAGE 2048 ///< Number page in data flash memory.
146 #error Nothing memory defined in CONFIG_DATA_FLASH are support.
152 * Data flash opcode commands.
156 * Read commands data flash.
160 #if CONFIG_DATA_FLASH == DATAFLASH_AT45DB081D || CONFIG_DATA_FLASH == AT45DB161D
161 DFO_READ_FLASH_MEM_BYTE = 0x0B, ///< Continuos array read.
162 #elif CONFIG_DATA_FLASH == DATAFLASH_AT45DB041B
163 DFO_READ_FLASH_MEM_BYTE = 0xE8, ///< Continuos array read.
165 #error No supported memory defined in CONFIG_DATA_FLASH.
167 DFO_READ_FLASH_MEM = 0xD2, ///< Main memory page read.
168 DFO_READ_BUFF1 = 0xD4, ///< SRAM buffer 1 read.
169 DFO_READ_BUFF2 = 0xD6, ///< SRAM buffer 2 read.
173 * Program and erase commands data flash.
176 DFO_WRITE_BUFF1 = 0x84, ///< SRAM buffer 1 write.
177 DFO_WRITE_BUFF2 = 0x87, ///< SRAM buffer 2 write.
178 DFO_WRITE_BUFF1_TO_MEM_E = 0x83, ///< Buffer 1 to main memory page program with build-in erase.
179 DFO_WRITE_BUFF2_TO_MEM_E = 0x86, ///< Buffer 2 to main memory page program with build-in erase.
180 DFO_WRITE_BUFF1_TO_MEM = 0x88, ///< Buffer 1 to main memory page program without build-in erase.
181 DFO_WRITE_BUFF2_TO_MEM = 0x89, ///< Buffer 2 to main memory page program without build-in erase.
182 DFO_ERASE_PAGE = 0x81, ///< Erase page.
183 DFO_ERASE_BLOCK = 0x50, ///< Erase block.
184 DFO_ERASE_SECTOR = 0x7C, ///< Erase sector.
185 DFO_WRITE_MEM_TR_BUFF1 = 0x82, ///< Write main memory page program through buffer 1.
186 DFO_WRITE_MEM_TR_BUFF2 = 0x85, ///< Write main memory page program through buffer 2.
190 * Additional commands data flash.
193 DFO_MOV_MEM_TO_BUFF1 = 0x53, ///< Main mmemory to buffer 1 transfer.
194 DFO_MOV_MEM_TO_BUFF2 = 0x55, ///< Main mmemory to buffer 2 transfer.
195 DFO_CMP_MEM_TO_BUFF1 = 0x60, ///< Main mmemory to buffer 1 compare.
196 DFO_CMP_MEM_TO_BUFF2 = 0x61, ///< Main mmemory to buffer 2 compare.
197 DFO_ARW_MEM_TR_BUFF1 = 0x58, ///< Auto page rewrite through buffer 1.
198 DFO_ARW_MEM_TR_BUFF2 = 0x59, ///< Auto page rewrite through buffer 2
199 DFO_PWR_DOWN = 0xB9, ///< Deep power-down.
200 DFO_RESUME_PWR_DOWN = 0xAB, ///< Resume from deep power-down.
201 DFO_READ_STATUS = 0xD7, ///< Status register read.
202 DFO_ID_DEV = 0x9F ///< Manufacturer and device ID read.
206 void dataflash_init(struct _KFile *fd);
207 void dataflash_test(void);
209 #endif /* DRV_DATAFLASH_H */