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29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
33 * \brief Function library for AT45DB081D Flash memory.
36 * \version $Id: dflash.h 15402 2007-04-10 09:10:56Z asterix $
37 * \author Daniele Basile <asterix@develer.com>
44 #include <kern/kfile.h>
45 #include <cfg/compiler.h>
49 #include <appconfig.h>
52 * Type definition for dflash memory.
54 typedef uint32_t dflashAddr_t;
55 typedef uint32_t dflashSize_t;
57 #define RESET_PULSE_WIDTH 10 // Width of reset pulse in usec.
58 #define BUSY_BIT 0x80 // Select a busy bit in status register.
59 #define CMP_BIT 0x40 // Select a compare bit in status register.
62 * Select 2,3,4,5 bits of status register, those
63 * bits indicate a id of density device (see datasheet for
66 #define GET_ID_DESITY_DEVICE(reg_stat)\
75 * \note RESET and WP are asserted when logic
79 #define RESET PC0 ///< Connect to RESET pin of flash memory
80 #define WP PC1 ///< Connect to WP pin of flash memory
81 #define DFLASH_PORT PORTC ///< Micro pin PORT register.
82 #define DFLASH_PIN PINC ///< Micro pin PIN register.
83 #define DFLASH_DDR DDRC ///< Micro pin DDR register.
91 #define RESET_LOW() do { DFLASH_PORT &= ~BV(RESET); } while(0)
92 #define RESET_HIGH() do { DFLASH_PORT |= BV(RESET); } while(0)
93 #define WP_LOW() do { DFLASH_PORT &= ~BV(WP); } while(0)
94 #define WP_HIGH() do { DFLASH_PORT |= BV(WP); } while(0)
100 * \note To reset flash memory it needs a pulse
101 * long about 10 usec. To do this we insert a
106 #define RESET_OUT() do { DFLASH_DDR |= BV(RESET); } while(0)
107 #define WP_OUT() do { DFLASH_DDR |= BV(WP); } while(0)
108 #define WRITE_ENABLE() WP_HIGH()
109 #define WRITE_DISABLE() WP_LOW()
110 #define RESET_ENABLE() RESET_LOW()
111 #define RESET_DISABLE() RESET_HIGH()
118 * \note Below are defined valid flash memory support to
119 * this drive. Every time we call dflash_init() function we check
120 * if memory defined are right (see dflash.c form more detail).
123 #define DFLASH_AT45DB041B 1
124 #define DFLASH_AT45DB081D 2
125 #define DFLASH_AT45DB161D 3
127 #if CONFIG_DATA_FLASH == DFLASH_AT45DB161D
128 #define DFLASH_ID_DEVICE_DENSITY 0xb ///< This indicate AT45DB161D data flah memory.
129 #define DFLASH_PAGE_SIZE 528 ///< Number of byte in one page.
130 #define DFLASH_PAGE_ADDRESS_BIT 10 ///< Number bit for addressing one page.
131 #define DFLASH_NUM_PAGE 4096 ///< Number page in data flash memory.
132 #elif CONFIG_DATA_FLASH == DFLASH_AT45DB081D
133 #define DFLASH_ID_DEVICE_DENSITY 0x9 ///< This indicate AT45DB081D data flah memory.
134 #define DFLASH_PAGE_SIZE 264 ///< Number of byte in one page.
135 #define DFLASH_PAGE_ADDRESS_BIT 9 ///< Number bit for addressing one page.
136 #define DFLASH_NUM_PAGE 4096 ///< Number page in data flash memory.
137 #elif CONFIG_DATA_FLASH == DFLASH_AT45DB041B
138 #define DFLASH_ID_DEVICE_DENSITY 0x7 ///< This indicate AT45DB041B data flah memory.
139 #define DFLASH_PAGE_SIZE 264 ///< Number of byte in one page.
140 #define DFLASH_PAGE_ADDRESS_BIT 9 ///< Number bit for addressing one page.
141 #define DFLASH_NUM_PAGE 2048 ///< Number page in data flash memory.
143 #error Nothing memory defined in CONFIG_DATA_FLASH are support.
149 * Data flash opcode commands.
153 * Read commands data flash.
157 #if CONFIG_DATA_FLASH == DFLASH_AT45DB081D || CONFIG_DATA_FLASH == AT45DB161D
158 DFO_READ_FLASH_MEM_BYTE = 0x0B, ///< Continuos array read.
159 #elif CONFIG_DATA_FLASH == DFLASH_AT45DB041B
160 DFO_READ_FLASH_MEM_BYTE = 0xE8, ///< Continuos array read.
162 #error No supported memory defined in CONFIG_DATA_FLASH.
164 DFO_READ_FLASH_MEM = 0xD2, ///< Main memory page read.
165 DFO_READ_BUFF1 = 0xD4, ///< SRAM buffer 1 read.
166 DFO_READ_BUFF2 = 0xD6, ///< SRAM buffer 2 read.
170 * Program and erase commands data flash.
173 DFO_WRITE_BUFF1 = 0x84, ///< SRAM buffer 1 write.
174 DFO_WRITE_BUFF2 = 0x87, ///< SRAM buffer 2 write.
175 DFO_WRITE_BUFF1_TO_MEM_E = 0x83, ///< Buffer 1 to main memory page program with build-in erase.
176 DFO_WRITE_BUFF2_TO_MEM_E = 0x86, ///< Buffer 2 to main memory page program with build-in erase.
177 DFO_WRITE_BUFF1_TO_MEM = 0x88, ///< Buffer 1 to main memory page program without build-in erase.
178 DFO_WRITE_BUFF2_TO_MEM = 0x89, ///< Buffer 2 to main memory page program without build-in erase.
179 DFO_ERASE_PAGE = 0x81, ///< Erase page.
180 DFO_ERASE_BLOCK = 0x50, ///< Erase block.
181 DFO_ERASE_SECTOR = 0x7C, ///< Erase sector.
182 DFO_WRITE_MEM_TR_BUFF1 = 0x82, ///< Write main memory page program through buffer 1.
183 DFO_WRITE_MEM_TR_BUFF2 = 0x85, ///< Write main memory page program through buffer 2.
187 * Additional commands data flash.
190 DFO_MOV_MEM_TO_BUFF1 = 0x53, ///< Main mmemory to buffer 1 transfer.
191 DFO_MOV_MEM_TO_BUFF2 = 0x55, ///< Main mmemory to buffer 2 transfer.
192 DFO_CMP_MEM_TO_BUFF1 = 0x60, ///< Main mmemory to buffer 1 compare.
193 DFO_CMP_MEM_TO_BUFF2 = 0x61, ///< Main mmemory to buffer 2 compare.
194 DFO_ARW_MEM_TR_BUFF1 = 0x58, ///< Auto page rewrite through buffer 1.
195 DFO_ARW_MEM_TR_BUFF2 = 0x59, ///< Auto page rewrite through buffer 2
196 DFO_PWR_DOWN = 0xB9, ///< Deep power-down.
197 DFO_RESUME_PWR_DOWN = 0xAB, ///< Resume from deep power-down.
198 DFO_READ_STATUS = 0xD7, ///< Status register read.
199 DFO_ID_DEV = 0x9F ///< Manufacturer and device ID read.
203 void dflash_init(struct _KFile *fd)
205 #endif /* DFLASH_H */