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29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
33 * \brief Function library for AT45DB081D Flash memory.
36 * \version $Id: dflash.h 15402 2007-04-10 09:10:56Z asterix $
37 * \author Daniele Basile <asterix@develer.com>
44 #include <appconfig.h>
46 #include <cfg/compiler.h>
53 * Type definition for dflash memory.
55 typedef uint32_t dflashAddr_t;
56 typedef uint32_t dflashSize_t;
58 #define RESET_PULSE_WIDTH 10 //Width of reset pulse in usec .
59 #define BUSY_BIT 0x80 //Select a busy bit in status register.
60 #define CMP_BIT 0x40 //Select a compare bit in status register.
63 * Select 2,3,4,5 bit of status register, that
64 * bit indicate a id of desity device (see datasheet for
67 #define GET_ID_DESITY_DEVICE(reg_stat)\
76 * \note RESET and WP are asserted when logic
80 #define RESET PC0 ///Connect to RESET pin of flash memory
81 #define WP PC1 ///Connect to WP pin of flash memory
82 #define DFLASH_PORT PORTC ///Micro pin PORT register.
83 #define DFLASH_PIN PINC ///Micro pin PIN register.
84 #define DFLASH_DDR DDRC ///Micro pin DDR register.
92 #define RESET_LOW() do { DFLASH_PORT &= ~BV(RESET); } while(0)
93 #define RESET_HIGH() do { DFLASH_PORT |= BV(RESET); } while(0)
94 #define WP_LOW() do { DFLASH_PORT &= ~BV(WP); } while(0)
95 #define WP_HIGH() do { DFLASH_PORT |= BV(WP); } while(0)
101 * \note To reset flash memory it need a pulse
102 * long about 10 usec, to do this we insert a
107 #define RESET_OUT() do { DFLASH_DDR |= BV(RESET); } while(0)
108 #define WP_OUT() do { DFLASH_DDR |= BV(WP); } while(0)
109 #define WRITE_ENABLE() WP_HIGH()
110 #define WRITE_DISABLE() WP_LOW()
111 #define RESET_ENABLE() RESET_LOW()
112 #define RESET_DISABLE() RESET_HIGH()
119 * \note Below are defined valid flash memory support to
120 * this drive. Every time we call dflash_init() function we check
121 * if memory defined are right (see dflash.c form more detail).
128 #if CONFIG_DATA_FLASH == AT45DB161D
129 #define DFLASH_ID_DEVICE_DENSITY 0xb ///This indicate AT45DB161D data flah memory.
130 #define DFLASH_PAGE_SIZE 528 ///Number of byte in one page.
131 #define DFLASH_PAGE_ADDRESS_BIT 10 ///Number bit for addressing one page.
132 #define DFLASH_NUM_PAGE 4096 ///Number page in data flash memory.
133 #elif CONFIG_DATA_FLASH == AT45DB081D
134 #define DFLASH_ID_DEVICE_DENSITY 0x9 ///This indicate AT45DB081D data flah memory.
135 #define DFLASH_PAGE_SIZE 264 ///Number of byte in one page.
136 #define DFLASH_PAGE_ADDRESS_BIT 9 ///Number bit for addressing one page.
137 #define DFLASH_NUM_PAGE 4096 ///Number page in data flash memory.
138 #elif CONFIG_DATA_FLASH == AT45DB041B
139 #define DFLASH_ID_DEVICE_DENSITY 0x7 ///This indicate AT45DB041B data flah memory.
140 #define DFLASH_PAGE_SIZE 264 ///Number of byte in one page.
141 #define DFLASH_PAGE_ADDRESS_BIT 9 ///Number bit for addressing one page.
142 #define DFLASH_NUM_PAGE 2048 ///Number page in data flash memory.
144 #error Nothing memory defined in CONFIG_DATA_FLASH are support.
150 * Data flash opcode commands.
154 * Read commands data flash.
158 #if CONFIG_DATA_FLASH == AT45DB081D || CONFIG_DATA_FLASH == AT45DB161D
159 DFO_READ_FLASH_MEM_BYTE = 0x0B, ///Continuos array read.
160 #elif CONFIG_DATA_FLASH == AT45DB041B
161 DFO_READ_FLASH_MEM_BYTE = 0xE8, ///Continuos array read.
163 #error Nothing memory define in CONFIG_DATA_FLASH are support.
165 DFO_READ_FLASH_MEM = 0xD2, ///Main memory page read.
166 DFO_READ_BUFF1 = 0xD4, ///SRAM buffer 1 read.
167 DFO_READ_BUFF2 = 0xD6, ///SRAM buffer 2 read.
171 * Program and erase commands data flash.
174 DFO_WRITE_BUFF1 = 0x84, ///SRAM buffer 1 write.
175 DFO_WRITE_BUFF2 = 0x87, ///SRAM buffer 2 write.
176 DFO_WRITE_BUFF1_TO_MEM_E = 0x83, ///Buffer 1 to main memory page program with build-in erase.
177 DFO_WRITE_BUFF2_TO_MEM_E = 0x86, ///Buffer 2 to main memory page program with build-in erase.
178 DFO_WRITE_BUFF1_TO_MEM = 0x88, ///Buffer 1 to main memory page program without build-in erase.
179 DFO_WRITE_BUFF2_TO_MEM = 0x89, ///Buffer 2 to main memory page program without build-in erase.
180 DFO_ERASE_PAGE = 0x81, ///Erase page.
181 DFO_ERASE_BLOCK = 0x50, ///Erase block.
182 DFO_ERASE_SECTOR = 0x7C, ///Erase sector.
183 DFO_WRITE_MEM_TR_BUFF1 = 0x82, ///Write main memory page program through buffer 1.
184 DFO_WRITE_MEM_TR_BUFF2 = 0x85, ///Write main memory page program through buffer 2.
188 * Additional commands data flash.
191 DFO_MOV_MEM_TO_BUFF1 = 0x53, ///Main mmemory to buffer 1 transfer.
192 DFO_MOV_MEM_TO_BUFF2 = 0x55, ///Main mmemory to buffer 2 transfer.
193 DFO_CMP_MEM_TO_BUFF1 = 0x60, ///Main mmemory to buffer 1 compare.
194 DFO_CMP_MEM_TO_BUFF2 = 0x61, ///Main mmemory to buffer 2 compare.
195 DFO_ARW_MEM_TR_BUFF1 = 0x58, ///Auto page rewrite through buffer 1.
196 DFO_ARW_MEM_TR_BUFF2 = 0x59, ///Auto page rewrite through buffer 2
197 DFO_PWR_DOWN = 0xB9, ///Deep power-down.
198 DFO_RESUME_PWR_DOWN = 0xAB, ///Resume from deep power-down.
199 DFO_READ_STATUS = 0xD7, ///Status register read.
200 DFO_ID_DEV = 0x9F ///Manufacturer and device ID read.
204 bool dflash_init(void);
205 void dflash_reset(void);
206 uint8_t dflash_stat(void);
208 uint8_t dflash_cmd(dflashAddr_t page_addr, dflashAddr_t byte_addr, DFlashOpcode opcode);
210 uint8_t dflash_read_byte(dflashAddr_t page_addr, dflashAddr_t byte_addr, DFlashOpcode opcode);
211 void dflash_read_block(dflashAddr_t page_addr, dflashAddr_t byte_addr, DFlashOpcode opcode, uint8_t *block, dflashSize_t len);
213 void dflash_write_byte(dflashAddr_t byte_addr, DFlashOpcode opcode, uint8_t data);
214 void dflash_write_block(dflashAddr_t byte_addr, DFlashOpcode opcode, uint8_t *block, dflashSize_t len);
216 #endif /* DFLASH_H */