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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief HSMCI driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
37 #include "dmac_sam3.h"
38 #include <drv/irq_cm3.h>
41 #include <cpu/power.h>
45 #include <mware/event.h>
59 #define DMAC_CHANNEL_CNT 6
60 struct DmacCh dmac_ch[] =
67 .ctrla = &DMAC_CTRLA0,
68 .ctrlb = &DMAC_CTRLB0,
75 .ctrla = &DMAC_CTRLA1,
76 .ctrlb = &DMAC_CTRLB1,
83 .ctrla = &DMAC_CTRLA2,
84 .ctrlb = &DMAC_CTRLB2,
91 .ctrla = &DMAC_CTRLA3,
92 .ctrlb = &DMAC_CTRLB3,
99 .ctrla = &DMAC_CTRLA4,
100 .ctrlb = &DMAC_CTRLB4,
107 .ctrla = &DMAC_CTRLA5,
108 .ctrlb = &DMAC_CTRLB5,
112 /* We use event to signal the end of conversion */
113 static Dmac dmac[DMAC_CHANNEL_CNT];
114 static uint8_t dmac_ch_enabled;
116 void dmac_setLLITransfer(int ch, DmacDesc *lli, uint32_t cfg)
119 reg32_t reg = DMAC_EBCISR;
122 *dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
123 *dmac_ch[ch].desc = (uint32_t)lli;
126 void dmac_setSources(int ch, uint32_t src, uint32_t dst)
130 *dmac_ch[ch].src = src;
131 *dmac_ch[ch].dst = dst;
132 *dmac_ch[ch].desc = 0;
135 void dmac_configureDmac(int ch, size_t transfer_size, uint32_t cfg, uint32_t ctrla, uint32_t ctrlb)
139 *dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT) | BV(DMAC_CFG_SOD);
140 *dmac_ch[ch].ctrla = ctrla | (transfer_size & DMAC_CTRLA_BTSIZE_MASK);
141 *dmac_ch[ch].ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
144 int dmac_start(int ch)
146 if (DMAC_CHSR & BV(ch))
148 dmac[ch].errors |= DMAC_ERR_CH_ALREDY_ON;
152 dmac_ch_enabled |= BV(ch);
156 void dmac_stop(int ch)
159 dmac_ch_enabled &= ~BV(ch);
162 int dmac_error(int ch)
164 uint32_t err = ((DMAC_EBCISR & 0x3F0000) | dmac[ch].errors);
169 static DECLARE_ISR(dmac_irq)
171 uint32_t status = DMAC_EBCISR;
172 uint32_t irq_ch = (status & (((dmac_ch_enabled |
173 (dmac_ch_enabled << DMAC_EBCIDR_ERR0) >> DMAC_EBCIDR_ERR0) |
174 (dmac_ch_enabled << DMAC_EBCIDR_CBTC0) >> DMAC_EBCIDR_CBTC0) & 0xFF));
176 for(int i = 0; i < 6; i++)
180 dmac[i].handler(status);
184 bool dmac_enableCh(int ch, dmac_handler_t handler)
186 ASSERT(ch <= DMAC_CHANNEL_CNT);
188 dmac_ch_enabled |= BV(ch);
191 dmac[ch].handler = handler;
192 DMAC_EBCIER |= (BV(ch) << DMAC_EBCIER_BTC0) | (BV(ch) << DMAC_EBCIDR_CBTC0) | (BV(ch) << DMAC_EBCIDR_ERR0);
193 kprintf("Init dmac ch[%08lx]\n", DMAC_EBCIMR);
202 memset(&dmac, 0, sizeof(dmac));
205 DMAC_EBCIDR = 0x3FFFFF;
208 pmc_periphEnable(DMAC_ID);
209 DMAC_EN = BV(DMAC_EN_ENABLE);
211 sysirq_setHandler(INT_DMAC, dmac_irq);