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29 * Copyright 2010,2011 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief EMAC driver for AT91SAM family with Davicom 9161A phy.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
37 * \author Stefano Fedrigo <aleph@develer.com>
40 #include "cfg/cfg_eth.h"
42 #define LOG_LEVEL ETH_LOG_LEVEL
43 #define LOG_FORMAT ETH_LOG_FORMAT
47 #include <cfg/debug.h>
49 #include <cfg/macros.h>
50 #include <cfg/compiler.h>
52 // TODO: unify includes
53 //#include <io/at91sam7.h>
55 //#include <io/include.h>
57 #include <drv/irq_cm3.h>
59 #include <cpu/power.h>
60 #include <cpu/types.h>
63 #include <drv/timer.h>
66 #include <mware/event.h>
72 #define EMAC_RX_INTS (BV(EMAC_RCOMP) | BV(EMAC_ROVR) | BV(EMAC_RXUBR))
73 #define EMAC_TX_INTS (BV(EMAC_TCOMP) | BV(EMAC_TXUBR) | BV(EMAC_RLEX))
76 * MAC address configuration (please change this in your project!).
78 * TODO: make this paramater user-configurable from the Wizard.
80 const uint8_t mac_addr[] = { 0x00, 0x23, 0x54, 0x6a, 0x77, 0x55 };
82 /* Silent Doxygen bug... */
85 * NOTE: this buffer should be declared as 'volatile' because it is read by the
86 * hardware. However, this is accessed only via memcpy() that should guarantee
87 * coherency when copying from/to buffers.
89 static uint8_t tx_buf[EMAC_TX_BUFFERS * EMAC_TX_BUFSIZ] ALIGNED(8);
90 static volatile BufDescriptor tx_buf_tab[EMAC_TX_DESCRIPTORS] ALIGNED(8);
93 * NOTE: this buffer should be declared as 'volatile' because it is wrote by
94 * the hardware. However, this is accessed only via memcpy() that should
95 * guarantee coherency when copying from/to buffers.
97 static uint8_t rx_buf[EMAC_RX_BUFFERS * EMAC_RX_BUFSIZ] ALIGNED(8);
98 static volatile BufDescriptor rx_buf_tab[EMAC_RX_DESCRIPTORS] ALIGNED(8);
101 static int tx_buf_idx;
102 static int tx_buf_offset;
103 static int rx_buf_idx;
105 static Event recv_wait, send_wait;
107 static DECLARE_ISR(emac_irqHandler)
109 /* Read interrupt status and disable interrupts. */
110 uint32_t isr = EMAC_ISR;
112 kprintf("irq: %x\n", isr);
114 /* Receiver interrupt */
115 if ((isr & EMAC_RX_INTS))
117 kprintf("emac: rx %x\n", isr);
118 if (isr & BV(EMAC_RCOMP))
119 event_do(&recv_wait);
120 EMAC_RSR = EMAC_RX_INTS;
122 /* Transmitter interrupt */
123 if (isr & EMAC_TX_INTS)
125 if (isr & BV(EMAC_TCOMP))
127 kprintf("emac: tcomp\n");
128 event_do(&send_wait);
130 if (isr & BV(EMAC_RLEX))
131 kprintf("emac: rlex\n");
132 EMAC_TSR = EMAC_TX_INTS;
138 * \brief Read contents of PHY register.
140 * \param reg PHY register number.
142 * \return Contents of the specified register.
144 static uint16_t phy_hw_read(uint8_t phy_addr, reg8_t reg)
147 EMAC_MAN = EMAC_SOF | EMAC_RW_READ
148 | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
149 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
152 // Wait until PHY logic completed.
153 while (!(EMAC_NSR & BV(EMAC_IDLE)))
156 // Get data from PHY maintenance register.
157 return (uint16_t)(EMAC_MAN & EMAC_DATA);
161 * \brief Write value to PHY register.
163 * \param reg PHY register number.
164 * \param val Value to write.
166 static void phy_hw_write(uint8_t phy_addr, reg8_t reg, uint16_t val)
168 // PHY write command.
169 EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE
170 | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
171 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
174 // Wait until PHY logic completed.
175 while (!(EMAC_NSR & BV(EMAC_IDLE)))
179 static int emac_reset(void)
186 PMC_PCER = BV(PIOA_ID);
187 PMC_PCER = BV(PIOB_ID);
188 PMC_PCER = BV(EMAC_ID);
190 // Disable TESTMODE and RMII
191 PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
192 PIOB_PUDR = BV(PHY_COL_RMII_BIT);
194 // Disable PHY power down.
195 PIOB_PER = BV(PHY_PWRDN_BIT);
196 PIOB_OER = BV(PHY_PWRDN_BIT);
197 PIOB_CODR = BV(PHY_PWRDN_BIT);
199 pmc_periphEnable(PIOA_ID);
200 pmc_periphEnable(PIOB_ID);
201 pmc_periphEnable(PIOC_ID);
202 pmc_periphEnable(PIOD_ID);
203 pmc_periphEnable(EMAC_ID);
205 // Disable TESTMODE and RMII
206 PIOC_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
208 // Disable PHY power down.
209 PIOD_PER = BV(PHY_PWRDN_BIT);
210 PIOD_OER = BV(PHY_PWRDN_BIT);
211 PIOD_CODR = BV(PHY_PWRDN_BIT);
214 // Toggle external hardware reset pin.
215 RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
216 RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
218 while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
221 // Configure MII ports.
223 PIOB_ASR = PHY_MII_PINS;
225 PIOB_PDR = PHY_MII_PINS;
227 // Enable receive and transmit clocks.
228 EMAC_USRIO = BV(EMAC_CLKEN);
230 PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
231 PIOB_PDR = PHY_MII_PINS_PORTB;
233 PIO_PERIPH_SEL(PIOC_BASE, PHY_MII_PINS_PORTC, PIO_PERIPH_A);
234 PIOC_PDR = PHY_MII_PINS_PORTC;
236 // Enable receive, transmit clocks and RMII mode.
237 EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
240 // Enable management port.
241 EMAC_NCR |= BV(EMAC_MPE);
242 EMAC_NCFGR |= EMAC_CLK_HCLK_64;
244 // Set local MAC address.
245 EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
246 (mac_addr[1] << 8) | mac_addr[0];
247 EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
249 // Wait for PHY ready
255 for (i = 0; i < 32; i++)
257 // Clear MII isolate.
258 phy_hw_read(i, NIC_PHY_BMCR);
259 phy_cr = phy_hw_read(i, NIC_PHY_BMCR);
261 phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
262 phy_hw_write(i, NIC_PHY_BMCR, phy_cr);
264 phy_cr = phy_hw_read(i, NIC_PHY_BMCR);
266 LOG_INFO("%s: PHY ID %d %#04x %#04x\n",
268 phy_hw_read(i, NIC_PHY_ID1), phy_hw_read(i, NIC_PHY_ID2));
274 // Clear MII isolate.
275 //phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMCR);
276 phy_cr = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMCR);
278 phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
279 phy_hw_write(NIC_PHY_ADDR, NIC_PHY_BMCR, phy_cr);
281 //phy_cr = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMCR);
283 LOG_INFO("%s: PHY ID %#04x %#04x\n",
285 phy_hw_read(NIC_PHY_ADDR, NIC_PHY_ID1), phy_hw_read(NIC_PHY_ADDR, NIC_PHY_ID2));
287 // Disable management port.
288 EMAC_NCR &= ~BV(EMAC_MPE);
293 static int emac_start(void)
298 for (i = 0; i < EMAC_RX_DESCRIPTORS; i++)
300 addr = (uint32_t)(rx_buf + (i * EMAC_RX_BUFSIZ));
301 rx_buf_tab[i].addr = addr & BUF_ADDRMASK;
303 rx_buf_tab[EMAC_RX_DESCRIPTORS - 1].addr |= RXBUF_WRAP;
305 for (i = 0; i < EMAC_TX_DESCRIPTORS; i++)
307 addr = (uint32_t)(tx_buf + (i * EMAC_TX_BUFSIZ));
308 tx_buf_tab[i].addr = addr & BUF_ADDRMASK;
309 tx_buf_tab[i].stat = TXS_USED;
311 tx_buf_tab[EMAC_TX_DESCRIPTORS - 1].stat = TXS_USED | TXS_WRAP;
313 /* Tell the EMAC where to find the descriptors. */
314 EMAC_RBQP = (uint32_t)rx_buf_tab;
315 EMAC_TBQP = (uint32_t)tx_buf_tab;
317 /* Clear receiver status. */
318 EMAC_RSR = BV(EMAC_OVR) | BV(EMAC_REC) | BV(EMAC_BNA);
320 /* Copy all frames and discard FCS. */
321 EMAC_NCFGR |= BV(EMAC_CAF) | BV(EMAC_DRFCS);
323 /* Enable receiver, transmitter and statistics. */
324 EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
329 ssize_t eth_putFrame(const uint8_t *buf, size_t len)
335 ASSERT(len <= sizeof(tx_buf));
337 /* Check if the transmit buffer is available */
338 while (!(tx_buf_tab[tx_buf_idx].stat & TXS_USED))
339 event_wait(&send_wait);
341 /* Copy the data into the buffer and prepare descriptor */
342 wr_len = MIN(len, (size_t)EMAC_TX_BUFSIZ - tx_buf_offset);
343 memcpy((uint8_t *)tx_buf_tab[tx_buf_idx].addr + tx_buf_offset,
345 tx_buf_offset += wr_len;
350 void eth_sendFrame(void)
352 tx_buf_tab[tx_buf_idx].stat = (tx_buf_offset & TXS_LENGTH_FRAME) |
354 ((tx_buf_idx == EMAC_TX_DESCRIPTORS - 1) ? TXS_WRAP : 0);
355 EMAC_NCR |= BV(EMAC_TSTART);
358 if (++tx_buf_idx >= EMAC_TX_DESCRIPTORS)
362 ssize_t eth_send(const uint8_t *buf, size_t len)
367 len = eth_putFrame(buf, len);
373 static void eth_buf_realign(int idx)
375 /* Empty buffer found. Realign. */
377 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
378 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
380 } while (idx != rx_buf_idx);
383 static size_t __eth_getFrameLen(void)
385 int idx, n = EMAC_RX_BUFFERS;
388 /* Skip empty buffers */
389 while ((n > 0) && !(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP))
391 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
397 LOG_INFO("no frame found\n");
400 /* Search the start of frame and cleanup fragments */
401 while ((n > 0) && (rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP) &&
402 !(rx_buf_tab[rx_buf_idx].stat & RXS_SOF))
404 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
405 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
411 LOG_INFO("no SOF found\n");
414 /* Search end of frame to evaluate the total frame size */
419 if (UNLIKELY(!(rx_buf_tab[idx].addr & RXBUF_OWNERSHIP)))
421 /* Empty buffer found. Realign. */
422 eth_buf_realign(idx);
425 if (rx_buf_tab[idx].stat & RXS_EOF)
426 return rx_buf_tab[idx].stat & RXS_LENGTH_FRAME;
427 if (UNLIKELY((idx != rx_buf_idx) &&
428 (rx_buf_tab[idx].stat & RXS_SOF)))
430 /* Another start of frame found. Realign. */
431 eth_buf_realign(idx);
434 if (++idx >= EMAC_RX_BUFFERS)
438 LOG_INFO("no EOF found\n");
442 size_t eth_getFrameLen(void)
446 /* Check if there is at least one available frame in the buffer */
449 len = __eth_getFrameLen();
452 /* Wait for RX interrupt */
453 event_wait(&recv_wait);
458 ssize_t eth_getFrame(uint8_t *buf, size_t len)
465 ASSERT(len <= sizeof(rx_buf));
467 /* Copy data from the RX buffer */
468 addr = (uint8_t *)(rx_buf_tab[rx_buf_idx].addr & BUF_ADDRMASK);
469 if (addr + len > &rx_buf[countof(rx_buf)])
471 size_t count = &rx_buf[countof(rx_buf)] - addr;
473 memcpy(buf, addr, count);
474 memcpy(buf + count, rx_buf, len - count);
478 memcpy(buf, addr, len);
480 /* Update descriptors */
483 if (len - rd_len >= EMAC_RX_BUFSIZ)
484 rd_len += EMAC_RX_BUFSIZ;
486 rd_len += len - rd_len;
487 if (UNLIKELY(!(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP)))
489 LOG_INFO("bad frame found\n");
492 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
493 if (++rx_buf_idx >= EMAC_RX_DESCRIPTORS)
500 ssize_t eth_recv(uint8_t *buf, size_t len)
504 len = MIN(len, eth_getFrameLen());
505 return len ? eth_getFrame(buf, len) : 0;
515 event_initGeneric(&recv_wait);
516 event_initGeneric(&send_wait);
518 // Register interrupt vector
519 IRQ_SAVE_DISABLE(flags);
521 /* Disable all emac interrupts */
522 EMAC_IDR = 0xFFFFFFFF;
525 // TODO: define sysirq_set...
526 /* Set the vector. */
527 AIC_SVR(EMAC_ID) = emac_irqHandler;
528 /* Initialize to edge triggered with defined priority. */
529 AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
530 /* Clear pending interrupt */
531 AIC_ICCR = BV(EMAC_ID);
532 /* Enable the system IRQ */
533 AIC_IECR = BV(EMAC_ID);
535 sysirq_setHandler(INT_EMAC, emac_irqHandler);
538 /* Enable interrupts */
539 EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS;