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33 * \brief EMAC driver for AT91SAM family with Davicom 9161A phy.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
37 * \author Stefano Fedrigo <aleph@develer.com>
40 #include "cfg/cfg_eth.h"
42 #define LOG_LEVEL ETH_LOG_LEVEL
43 #define LOG_FORMAT ETH_LOG_FORMAT
47 #include <cfg/debug.h>
49 #include <cfg/macros.h>
50 #include <cfg/compiler.h>
52 // TODO: unify includes
53 //#include <io/at91sam7.h>
55 //#include <io/include.h>
57 #include <drv/irq_cm3.h>
59 #include <cpu/power.h>
60 #include <cpu/types.h>
63 #include <drv/timer.h>
66 #include <mware/event.h>
72 #define EMAC_RX_INTS (BV(EMAC_RCOMP) | BV(EMAC_ROVR) | BV(EMAC_RXUBR))
73 #define EMAC_TX_INTS (BV(EMAC_TCOMP) | BV(EMAC_TXUBR) | BV(EMAC_RLEX))
75 /* Silent Doxygen bug... */
78 * NOTE: this buffer should be declared as 'volatile' because it is read by the
79 * hardware. However, this is accessed only via memcpy() that should guarantee
80 * coherency when copying from/to buffers.
82 static uint8_t tx_buf[EMAC_TX_BUFFERS * EMAC_TX_BUFSIZ] ALIGNED(8);
83 static volatile BufDescriptor tx_buf_tab[EMAC_TX_DESCRIPTORS] ALIGNED(8);
86 * NOTE: this buffer should be declared as 'volatile' because it is wrote by
87 * the hardware. However, this is accessed only via memcpy() that should
88 * guarantee coherency when copying from/to buffers.
90 static uint8_t rx_buf[EMAC_RX_BUFFERS * EMAC_RX_BUFSIZ] ALIGNED(8);
91 static volatile BufDescriptor rx_buf_tab[EMAC_RX_DESCRIPTORS] ALIGNED(8);
94 static int tx_buf_idx;
95 static int tx_buf_offset;
96 static int rx_buf_idx;
98 static Event recv_wait, send_wait;
100 static DECLARE_ISR(emac_irqHandler)
102 /* Read interrupt status and disable interrupts. */
103 uint32_t isr = EMAC_ISR;
105 /* Receiver interrupt */
106 if ((isr & EMAC_RX_INTS))
108 if (isr & BV(EMAC_RCOMP))
109 event_do(&recv_wait);
110 EMAC_RSR = EMAC_RX_INTS;
112 /* Transmitter interrupt */
113 if (isr & EMAC_TX_INTS)
115 if (isr & BV(EMAC_TCOMP))
116 event_do(&send_wait);
117 EMAC_TSR = EMAC_TX_INTS;
123 * \brief Read contents of PHY register.
125 * \param reg PHY register number.
127 * \return Contents of the specified register.
129 static uint16_t phy_hw_read(uint8_t phy_addr, reg8_t reg)
132 EMAC_MAN = EMAC_SOF | EMAC_RW_READ
133 | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
134 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
137 // Wait until PHY logic completed.
138 while (!(EMAC_NSR & BV(EMAC_IDLE)))
141 // Get data from PHY maintenance register.
142 return (uint16_t)(EMAC_MAN & EMAC_DATA);
147 * \brief Write value to PHY register.
149 * \param reg PHY register number.
150 * \param val Value to write.
152 static void phy_hw_write(uint8_t phy_addr, reg8_t reg, uint16_t val)
154 // PHY write command.
155 EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE
156 | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
157 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
160 // Wait until PHY logic completed.
161 while (!(EMAC_NSR & BV(EMAC_IDLE)))
167 * Check link speed and duplex as negotiated by the PHY
168 * and configure CPU EMAC accordingly.
169 * Requires active PHY maintenance mode.
171 static void emac_autoNegotiation(void)
176 // Wait for auto-negotation to complete
177 start = timer_clock();
179 reg = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMSR);
180 if (timer_clock() - start > 2000)
182 kprintf("eth error: auto-negotiation timeout\n");
186 while (!(reg & NIC_PHY_BMSR_ANCOMPL));
188 reg = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_ANLPAR);
190 if ((reg & NIC_PHY_ANLPAR_TX_FDX) || (reg & NIC_PHY_ANLPAR_TX_HDX))
192 LOG_INFO("eth: 100BASE-TX\n");
193 EMAC_NCFGR |= BV(EMAC_SPD);
197 LOG_INFO("eth: 10BASE-T\n");
198 EMAC_NCFGR &= ~BV(EMAC_SPD);
201 if ((reg & NIC_PHY_ANLPAR_TX_FDX) || (reg & NIC_PHY_ANLPAR_10_FDX))
203 LOG_INFO("eth: full duplex\n");
204 EMAC_NCFGR |= BV(EMAC_FD);
208 LOG_INFO("eth: half duplex\n");
209 EMAC_NCFGR &= ~BV(EMAC_FD);
214 static int emac_reset(void)
218 PMC_PCER = BV(PIOA_ID);
219 PMC_PCER = BV(PIOB_ID);
220 PMC_PCER = BV(EMAC_ID);
222 // Disable TESTMODE and RMII
223 PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
224 PIOB_PUDR = BV(PHY_COL_RMII_BIT);
226 // Disable PHY power down.
227 PIOB_PER = BV(PHY_PWRDN_BIT);
228 PIOB_OER = BV(PHY_PWRDN_BIT);
229 PIOB_CODR = BV(PHY_PWRDN_BIT);
231 pmc_periphEnable(PIOA_ID);
232 pmc_periphEnable(PIOB_ID);
233 pmc_periphEnable(PIOC_ID);
234 pmc_periphEnable(PIOD_ID);
235 pmc_periphEnable(EMAC_ID);
238 PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
241 // Toggle external hardware reset pin.
242 RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
243 RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
245 while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
248 // Configure MII ports.
250 PIOB_ASR = PHY_MII_PINS;
252 PIOB_PDR = PHY_MII_PINS;
254 // Enable receive and transmit clocks.
255 EMAC_USRIO = BV(EMAC_CLKEN);
257 PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
258 PIOB_PDR = PHY_MII_PINS_PORTB;
260 // Enable receive, transmit clocks and RMII mode.
261 EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
264 // Enable management port.
265 EMAC_NCR |= BV(EMAC_MPE);
266 EMAC_NCFGR |= EMAC_CLK_HCLK_64;
268 // Set local MAC address.
269 EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
270 (mac_addr[1] << 8) | mac_addr[0];
271 EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
273 emac_autoNegotiation();
275 // Disable management port.
276 EMAC_NCR &= ~BV(EMAC_MPE);
282 static int emac_start(void)
287 for (i = 0; i < EMAC_RX_DESCRIPTORS; i++)
289 addr = (uint32_t)(rx_buf + (i * EMAC_RX_BUFSIZ));
290 rx_buf_tab[i].addr = addr & BUF_ADDRMASK;
292 rx_buf_tab[EMAC_RX_DESCRIPTORS - 1].addr |= RXBUF_WRAP;
294 for (i = 0; i < EMAC_TX_DESCRIPTORS; i++)
296 addr = (uint32_t)(tx_buf + (i * EMAC_TX_BUFSIZ));
297 tx_buf_tab[i].addr = addr & BUF_ADDRMASK;
298 tx_buf_tab[i].stat = TXS_USED;
300 tx_buf_tab[EMAC_TX_DESCRIPTORS - 1].stat = TXS_USED | TXS_WRAP;
302 /* Tell the EMAC where to find the descriptors. */
303 EMAC_RBQP = (uint32_t)rx_buf_tab;
304 EMAC_TBQP = (uint32_t)tx_buf_tab;
306 /* Clear receiver status. */
307 EMAC_RSR = BV(EMAC_OVR) | BV(EMAC_REC) | BV(EMAC_BNA);
309 /* Copy all frames and discard FCS. */
310 EMAC_NCFGR |= BV(EMAC_CAF) | BV(EMAC_DRFCS);
312 /* Enable receiver, transmitter and statistics. */
313 EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
318 ssize_t eth_putFrame(const uint8_t *buf, size_t len)
324 ASSERT(len <= sizeof(tx_buf));
326 /* Check if the transmit buffer is available */
327 while (!(tx_buf_tab[tx_buf_idx].stat & TXS_USED))
328 event_wait(&send_wait);
330 /* Copy the data into the buffer and prepare descriptor */
331 wr_len = MIN(len, (size_t)EMAC_TX_BUFSIZ - tx_buf_offset);
332 memcpy((uint8_t *)tx_buf_tab[tx_buf_idx].addr + tx_buf_offset,
334 tx_buf_offset += wr_len;
339 void eth_sendFrame(void)
341 tx_buf_tab[tx_buf_idx].stat = (tx_buf_offset & TXS_LENGTH_FRAME) |
343 ((tx_buf_idx == EMAC_TX_DESCRIPTORS - 1) ? TXS_WRAP : 0);
344 EMAC_NCR |= BV(EMAC_TSTART);
347 if (++tx_buf_idx >= EMAC_TX_DESCRIPTORS)
351 ssize_t eth_send(const uint8_t *buf, size_t len)
356 len = eth_putFrame(buf, len);
362 static void eth_buf_realign(int idx)
364 /* Empty buffer found. Realign. */
366 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
367 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
369 } while (idx != rx_buf_idx);
372 static size_t __eth_getFrameLen(void)
374 int idx, n = EMAC_RX_BUFFERS;
377 /* Skip empty buffers */
378 while ((n > 0) && !(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP))
380 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
386 LOG_INFO("no frame found\n");
389 /* Search the start of frame and cleanup fragments */
390 while ((n > 0) && (rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP) &&
391 !(rx_buf_tab[rx_buf_idx].stat & RXS_SOF))
393 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
394 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
400 LOG_INFO("no SOF found\n");
403 /* Search end of frame to evaluate the total frame size */
408 if (UNLIKELY(!(rx_buf_tab[idx].addr & RXBUF_OWNERSHIP)))
410 /* Empty buffer found. Realign. */
411 eth_buf_realign(idx);
414 if (rx_buf_tab[idx].stat & RXS_EOF)
415 return rx_buf_tab[idx].stat & RXS_LENGTH_FRAME;
416 if (UNLIKELY((idx != rx_buf_idx) &&
417 (rx_buf_tab[idx].stat & RXS_SOF)))
419 /* Another start of frame found. Realign. */
420 eth_buf_realign(idx);
423 if (++idx >= EMAC_RX_BUFFERS)
427 LOG_INFO("no EOF found\n");
431 size_t eth_getFrameLen(void)
435 /* Check if there is at least one available frame in the buffer */
438 len = __eth_getFrameLen();
441 /* Wait for RX interrupt */
442 event_wait(&recv_wait);
447 ssize_t eth_getFrame(uint8_t *buf, size_t len)
454 ASSERT(len <= sizeof(rx_buf));
456 /* Copy data from the RX buffer */
457 addr = (uint8_t *)(rx_buf_tab[rx_buf_idx].addr & BUF_ADDRMASK);
458 if (addr + len > &rx_buf[countof(rx_buf)])
460 size_t count = &rx_buf[countof(rx_buf)] - addr;
462 memcpy(buf, addr, count);
463 memcpy(buf + count, rx_buf, len - count);
467 memcpy(buf, addr, len);
469 /* Update descriptors */
472 if (len - rd_len >= EMAC_RX_BUFSIZ)
473 rd_len += EMAC_RX_BUFSIZ;
475 rd_len += len - rd_len;
476 if (UNLIKELY(!(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP)))
478 LOG_INFO("bad frame found\n");
481 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
482 if (++rx_buf_idx >= EMAC_RX_DESCRIPTORS)
489 ssize_t eth_recv(uint8_t *buf, size_t len)
493 len = MIN(len, eth_getFrameLen());
494 return len ? eth_getFrame(buf, len) : 0;
504 event_initGeneric(&recv_wait);
505 event_initGeneric(&send_wait);
507 // Register interrupt vector
508 IRQ_SAVE_DISABLE(flags);
510 /* Disable all emac interrupts */
511 EMAC_IDR = 0xFFFFFFFF;
514 // TODO: define sysirq_set...
515 /* Set the vector. */
516 AIC_SVR(EMAC_ID) = emac_irqHandler;
517 /* Initialize to edge triggered with defined priority. */
518 AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
519 /* Clear pending interrupt */
520 AIC_ICCR = BV(EMAC_ID);
521 /* Enable the system IRQ */
522 AIC_IECR = BV(EMAC_ID);
524 sysirq_setHandler(INT_EMAC, emac_irqHandler);
527 /* Enable interrupts */
528 EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS;