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33 * \brief EMAC driver for AT91SAM family with Davicom 9161A phy, interface.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
37 * \author Stefano Fedrigo <aleph@develer.com>
43 // Settings and definition for DAVICOM 9161A
45 #define NIC_PHY_ADDR 0
48 #define NIC_PHY_BMCR 0x00 // Basic mode control register.
49 #define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test.
50 #define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode.
51 #define NIC_PHY_BMCR_ANEGSTART 0x0200 // Restart auto negotiation.
52 #define NIC_PHY_BMCR_ISOLATE 0x0400 // Isolate from MII.
53 #define NIC_PHY_BMCR_PWRDN 0x0800 // Power-down.
54 #define NIC_PHY_BMCR_ANEGENA 0x1000 // Enable auto negotiation.
55 #define NIC_PHY_BMCR_100MBPS 0x2000 // Select 100 Mbps.
56 #define NIC_PHY_BMCR_LOOPBACK 0x4000 // Enable loopback mode.
57 #define NIC_PHY_BMCR_RESET 0x8000 // Software reset.
59 #define NIC_PHY_BMSR 0x01 // Basic mode status register.
60 #define NIC_PHY_BMSR_ANCOMPL 0x0020 // Auto negotiation complete.
61 #define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation
62 #define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status.
64 #define NIC_PHY_ID1 0x02 // PHY identifier register 1.
65 #define NIC_PHY_ID2 0x03 // PHY identifier register 2.
66 #define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register.
67 #define NIC_PHY_ANLPAR 0x05 // Auto negotiation link partner availability register.
68 #define NIC_PHY_ANER 0x06 // Auto negotiation expansion register.
73 * Pin definition for DAVICOM 9161A.
74 * See schematics for AT91SAM7X-EK evalution board.
77 #define PHY_TXCLK_ISOLATE_BIT 0
78 #define PHY_REFCLK_XT2_BIT 0
79 #define PHY_TXEN_BIT 1
80 #define PHY_TXD0_BIT 2
81 #define PHY_TXD1_BIT 3
82 #define PHY_CRS_AD4_BIT 4
83 #define PHY_RXD0_AD0_BIT 5
84 #define PHY_RXD1_AD1_BIT 6
85 #define PHY_RXER_RXD4_RPTR_BIT 7
87 #define PHY_MDIO_BIT 9
88 #define PHY_TXD2_BIT 10
89 #define PHY_TXD3_BIT 11
90 #define PHY_TXER_TXD4_BIT 12
91 #define PHY_RXD2_AD2_BIT 13
92 #define PHY_RXD3_AD3_BIT 14
93 #define PHY_RXDV_TESTMODE_BIT 15
94 #define PHY_COL_RMII_BIT 16
95 #define PHY_RXCLK_10BTSER_BIT 17
96 #define PHY_PWRDN_BIT 18
97 #define PHY_MDINTR_BIT 26
99 #define PHY_MII_PINS \
100 BV(PHY_REFCLK_XT2_BIT) \
104 | BV(PHY_CRS_AD4_BIT) \
105 | BV(PHY_RXD0_AD0_BIT) \
106 | BV(PHY_RXD1_AD1_BIT) \
107 | BV(PHY_RXER_RXD4_RPTR_BIT) \
112 | BV(PHY_TXER_TXD4_BIT) \
113 | BV(PHY_RXD2_AD2_BIT) \
114 | BV(PHY_RXD3_AD3_BIT) \
115 | BV(PHY_RXDV_TESTMODE_BIT) \
116 | BV(PHY_COL_RMII_BIT) \
117 | BV(PHY_RXCLK_10BTSER_BIT)
122 * Pin definition for DAVICOM 9161A.
123 * See schematics for SAM3X-EK evalution board.
126 #define PHY_TXCLK_ISOLATE_BIT 0
127 #define PHY_REFCLK_XT2_BIT 0
128 #define PHY_TXEN_BIT 1
129 #define PHY_TXD0_BIT 2
130 #define PHY_TXD1_BIT 3
131 #define PHY_RXD0_AD0_BIT 5
132 #define PHY_RXD1_AD1_BIT 6
133 #define PHY_RXER_RXD4_RPTR_BIT 7
134 #define PHY_MDC_BIT 8
135 #define PHY_MDIO_BIT 9
137 #define PHY_RXDV_TESTMODE_BIT 10
139 #define PHY_MDINTR_BIT 5
140 // Port D -- FIXME: Only on which revision?
141 #define PHY_PWRDN_BIT 18
143 #define PHY_MII_PINS_PORTB \
144 BV(PHY_REFCLK_XT2_BIT) \
148 | BV(PHY_RXD0_AD0_BIT) \
149 | BV(PHY_RXD1_AD1_BIT) \
150 | BV(PHY_RXER_RXD4_RPTR_BIT) \
154 #define PHY_MII_PINS_PORTC \
155 BV(PHY_RXDV_TESTMODE_BIT)
157 #endif /* CPU_ARM_AT91 */
161 #define EMAC_TX_BUFSIZ 1518 //!!! Don't change this
162 #define EMAC_TX_BUFFERS 1 //!!! Don't change this
163 #define EMAC_TX_DESCRIPTORS EMAC_TX_BUFFERS
165 #define EMAC_RX_BUFFERS 32 //!!! Don't change this
166 #define EMAC_RX_BUFSIZ 128 //!!! Don't change this
167 #define EMAC_RX_DESCRIPTORS EMAC_RX_BUFFERS
169 // Flag to manage local tx buffer
170 #define TXS_USED 0x80000000 //Used buffer.
171 #define TXS_WRAP 0x40000000 //Last descriptor.
172 #define TXS_ERROR 0x20000000 //Retry limit exceeded.
173 #define TXS_UNDERRUN 0x10000000 //Transmit underrun.
174 #define TXS_NO_BUFFER 0x08000000 //Buffer exhausted.
175 #define TXS_NO_CRC 0x00010000 //CRC not appended.
176 #define TXS_LAST_BUFF 0x00008000 //Last buffer of frame.
177 #define TXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS.
179 // Flag to manage local rx buffer
180 #define RXBUF_OWNERSHIP 0x00000001
181 #define RXBUF_WRAP 0x00000002
183 #define BUF_ADDRMASK 0xFFFFFFFC
185 #define RXS_BROADCAST_ADDR 0x80000000 // Broadcast address detected.
186 #define RXS_MULTICAST_HASH 0x40000000 // Multicast hash match.
187 #define RXS_UNICAST_HASH 0x20000000 // Unicast hash match.
188 #define RXS_EXTERNAL_ADDR 0x10000000 // External address match.
189 #define RXS_SA1_ADDR 0x04000000 // Specific address register 1 match.
190 #define RXS_SA2_ADDR 0x02000000 // Specific address register 2 match.
191 #define RXS_SA3_ADDR 0x01000000 // Specific address register 3 match.
192 #define RXS_SA4_ADDR 0x00800000 // Specific address register 4 match.
193 #define RXS_TYPE_ID 0x00400000 // Type ID match.
194 #define RXS_VLAN_TAG 0x00200000 // VLAN tag detected.
195 #define RXS_PRIORITY_TAG 0x00100000 // Priority tag detected.
196 #define RXS_VLAN_PRIORITY 0x000E0000 // VLAN priority.
197 #define RXS_CFI_IND 0x00010000 // Concatenation format indicator.
198 #define RXS_EOF 0x00008000 // End of frame.
199 #define RXS_SOF 0x00004000 // Start of frame.
200 #define RXS_RBF_OFFSET 0x00003000 // Receive buffer offset mask.
201 #define RXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS.
203 #define EMAC_RSR_BITS (BV(EMAC_BNA) | BV(EMAC_REC) | BV(EMAC_OVR))
204 #define EMAC_TSR_BITS (BV(EMAC_UBR) | BV(EMAC_COL) | BV(EMAC_RLES) | \
205 BV(EMAC_BEX) | BV(EMAC_COMP) | BV(EMAC_UND))
207 typedef struct BufDescriptor
209 volatile uint32_t addr;
210 volatile uint32_t stat;
213 #endif /* ETH_SAM3_H */