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29 * Copyright 2003, 2004, 2005 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the AVR ATMega TWI (implementation)
35 * \author Stefano Fedrigo <aleph@develer.com>
36 * \author Bernie Innocenti <bernie@codewiz.org>
37 * \author Daniele Basile <asterix@develer.com>
40 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
42 #include "cfg/cfg_i2c.h"
44 #define LOG_LEVEL I2C_LOG_LEVEL
45 #define LOG_FORMAT I2C_LOG_FORMAT
49 #include <cfg/debug.h>
50 #include <cfg/macros.h> // BV()
51 #include <cfg/module.h>
53 #include <cpu/detect.h>
55 #include <drv/timer.h>
58 #include <cpu/power.h>
60 #include <compat/twi.h>
63 /* Wait for TWINT flag set: bus is ready */
64 #define WAIT_TWI_READY do {} while (!(TWCR & BV(TWINT)))
67 * Send START condition on the bus.
69 * \return true on success, false otherwise.
71 static bool i2c_builtin_start(void)
73 TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
76 if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
79 LOG_ERR("!TW_(REP)START: %x\n", TWSR);
85 * Send START condition and select slave for write.
86 * \c id is the device id comprehensive of address left shifted by 1.
87 * The LSB of \c id is ignored and reset to 0 for write operation.
89 * \return true on success, false otherwise.
91 bool i2c_builtin_start_w(uint8_t id)
94 * Loop on the select write sequence: when the eeprom is busy
95 * writing previously sent data it will reply to the SLA_W
96 * control byte with a NACK. In this case, we must
97 * keep trying until the eeprom responds with an ACK.
99 ticks_t start = timer_clock();
100 while (i2c_builtin_start())
102 TWDR = id & ~I2C_READBIT;
103 TWCR = BV(TWINT) | BV(TWEN);
106 if (TW_STATUS == TW_MT_SLA_ACK)
108 else if (TW_STATUS != TW_MT_SLA_NACK)
110 LOG_ERR("!TW_MT_SLA_(N)ACK: %x\n", TWSR);
113 else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
115 LOG_ERR("Timeout on TWI_MT_START\n");
125 * Send START condition and select slave for read.
126 * \c id is the device id comprehensive of address left shifted by 1.
127 * The LSB of \c id is ignored and set to 1 for read operation.
129 * \return true on success, false otherwise.
131 bool i2c_builtin_start_r(uint8_t id)
133 if (i2c_builtin_start())
135 TWDR = id | I2C_READBIT;
136 TWCR = BV(TWINT) | BV(TWEN);
139 if (TW_STATUS == TW_MR_SLA_ACK)
142 LOG_ERR("!TW_MR_SLA_ACK: %x\n", TWSR);
150 * Send STOP condition.
152 void i2c_builtin_stop(void)
154 TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
159 * Put a single byte in master transmitter mode
160 * to the selected slave device through the TWI bus.
162 * \return true on success, false on error.
164 bool i2c_builtin_put(const uint8_t data)
167 TWCR = BV(TWINT) | BV(TWEN);
169 if (TW_STATUS != TW_MT_DATA_ACK)
171 LOG_ERR("!TW_MT_DATA_ACK: %x\n", TWSR);
178 * Get 1 byte from slave in master transmitter mode
179 * to the selected slave device through the TWI bus.
180 * If \a ack is true issue a ACK after getting the byte,
181 * otherwise a NACK is issued.
183 * \return the byte read if ok, EOF on errors.
185 int i2c_builtin_get(bool ack)
187 TWCR = BV(TWINT) | BV(TWEN) | (ack ? BV(TWEA) : 0);
192 if (TW_STATUS != TW_MR_DATA_ACK)
194 LOG_ERR("!TW_MR_DATA_ACK: %x\n", TWSR);
200 if (TW_STATUS != TW_MR_DATA_NACK)
202 LOG_ERR("!TW_MR_DATA_NACK: %x\n", TWSR);
207 /* avoid sign extension */
208 return (int)(uint8_t)TWDR;
215 * Initialize TWI module.
217 void i2c_builtin_init(void)
221 * This is pretty useless according to AVR's datasheet,
222 * but it helps us driving the TWI data lines on boards
223 * where the bus pull-up resistors are missing. This is
224 * probably due to some unwanted interaction between the
225 * port pin and the TWI lines.
227 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
228 PORTD |= BV(PD0) | BV(PD1);
229 DDRD |= BV(PD0) | BV(PD1);
230 #elif CPU_AVR_ATMEGA8
231 PORTC |= BV(PC4) | BV(PC5);
232 DDRC |= BV(PC4) | BV(PC5);
233 #elif CPU_AVR_ATMEGA32
234 PORTC |= BV(PC1) | BV(PC0);
235 DDRC |= BV(PC1) | BV(PC0);
237 #error Unsupported architecture
242 * F = CPU_FREQ / (16 + 2*TWBR * 4^TWPS)
244 #ifndef CONFIG_I2C_FREQ
245 #warning Using default value of 300000L for CONFIG_I2C_FREQ
246 #define CONFIG_I2C_FREQ 300000L /* ~300 kHz */
248 #define TWI_PRESC 1 /* 4 ^ TWPS */
250 TWBR = (CPU_FREQ / (2 * CONFIG_I2C_FREQ * TWI_PRESC)) - (8 / TWI_PRESC);
267 /* Wait for TWINT flag set: bus is ready */
268 #define WAIT_READY() \
270 while (!(TWCR & BV(TWINT))) \
275 * Send START condition on the bus.
277 INLINE bool i2c_hw_start(void)
279 TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
282 if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
289 * Send STOP condition.
291 INLINE void i2c_hw_stop(void)
293 TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
296 static void i2c_avr_start(I2c *i2c, uint16_t slave_addr)
299 * Loop on the select write sequence: when the eeprom is busy
300 * writing previously sent data it will reply to the SLA_W
301 * control byte with a NACK. In this case, we must
302 * keep trying until the slave responds with an ACK.
304 ticks_t start = timer_clock();
305 while (i2c_hw_start())
308 uint8_t sla_nack = 0;
309 if (I2C_TEST_START(i2c->flags) == I2C_START_W)
311 TWDR = slave_addr & ~I2C_READBIT;
312 sla_ack = TW_MT_SLA_ACK;
313 sla_nack = TW_MT_SLA_NACK;
317 TWDR = slave_addr | I2C_READBIT;
318 sla_ack = TW_MR_SLA_ACK;
319 sla_nack = TW_MR_SLA_NACK;
322 TWCR = BV(TWINT) | BV(TWEN);
325 if (TW_STATUS == sla_ack)
327 else if (TW_STATUS != sla_nack)
329 LOG_ERR("Start addr NACK[%x]\n", TWSR);
330 i2c->errors |= I2C_NO_ACK;
334 else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
336 LOG_ERR("Start timeout\n");
337 i2c->errors |= I2C_START_TIMEOUT;
343 LOG_ERR("I2c error\n");
344 i2c->errors |= I2C_ERR;
348 static void i2c_avr_putc(I2c *i2c, const uint8_t data)
352 TWCR = BV(TWINT) | BV(TWEN);
355 if (TW_STATUS != TW_MT_DATA_ACK)
357 LOG_ERR("Data nack[%x]\n", TWSR);
358 i2c->errors |= I2C_DATA_NACK;
362 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
366 static uint8_t i2c_avr_getc(I2c *i2c)
368 uint8_t data_flag = 0;
369 if (i2c->xfer_size == 1)
371 TWCR = BV(TWINT) | BV(TWEN);
372 data_flag = TW_MR_DATA_NACK;
376 TWCR = BV(TWINT) | BV(TWEN) | BV(TWEA);
377 data_flag = TW_MR_DATA_ACK;
382 if (TW_STATUS != data_flag)
384 LOG_ERR("Data nack[%x]\n", TWSR);
385 i2c->errors |= I2C_DATA_NACK;
393 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
400 static const I2cVT i2c_avr_vt =
402 .start = i2c_avr_start,
403 .getc = i2c_avr_getc,
404 .putc = i2c_avr_putc,
405 .write = i2c_genericWrite,
406 .read = i2c_genericRead,
409 struct I2cHardware i2c_avr_hw[] =
416 * Initialize I2C module.
418 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
420 i2c->hw = &i2c_avr_hw[dev];
421 i2c->vt = &i2c_avr_vt;
425 * This is pretty useless according to AVR's datasheet,
426 * but it helps us driving the TWI data lines on boards
427 * where the bus pull-up resistors are missing. This is
428 * probably due to some unwanted interaction between the
429 * port pin and the TWI lines.
431 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
432 PORTD |= BV(PD0) | BV(PD1);
433 DDRD |= BV(PD0) | BV(PD1);
434 #elif CPU_AVR_ATMEGA8
435 PORTC |= BV(PC4) | BV(PC5);
436 DDRC |= BV(PC4) | BV(PC5);
437 #elif CPU_AVR_ATMEGA32
438 PORTC |= BV(PC1) | BV(PC0);
439 DDRC |= BV(PC1) | BV(PC0);
441 #error Unsupported architecture
446 * F = CPU_FREQ / (16 + 2*TWBR * 4^TWPS)
449 #define TWI_PRESC 1 /* 4 ^ TWPS */
451 TWBR = (CPU_FREQ / (2 * clock * TWI_PRESC)) - (8 / TWI_PRESC);