4 * This file is part of BeRTOS.
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief TWI driver for SAM3 (implementation)
35 * Only master mode is supported.
37 * \author Stefano Fedrigo <aleph@develer.com>
41 #include "cfg/cfg_i2c.h"
43 #define LOG_LEVEL I2C_LOG_LEVEL
44 #define LOG_FORMAT I2C_LOG_FORMAT
48 #include <hw/hw_cpufreq.h> // CPU_FREQ
49 #include <cfg/debug.h>
50 #include <cfg/macros.h> // BV()
51 #include <cfg/module.h>
52 #include <cpu/detect.h>
54 #include <cpu/power.h>
55 #include <drv/timer.h>
67 INLINE bool waitTxRdy(I2c *i2c, time_t ms_timeout)
69 ticks_t start = timer_clock();
71 while (!(HWREG(i2c->hw->base + TWI_SR_OFF) & TWI_SR_TXRDY))
73 if (timer_clock() - start > ms_to_ticks(ms_timeout))
81 INLINE bool waitRxRdy(I2c *i2c, time_t ms_timeout)
83 ticks_t start = timer_clock();
85 while (!(HWREG(i2c->hw->base + TWI_SR_OFF) & TWI_SR_RXRDY))
87 if (timer_clock() - start > ms_to_ticks(ms_timeout))
95 INLINE void waitXferComplete(I2c *i2c)
97 while (!(HWREG(i2c->hw->base + TWI_SR_OFF) & TWI_SR_TXCOMP))
102 * Send STOP condition.
104 INLINE void sendStop(I2c *i2c)
106 HWREG(i2c->hw->base + TWI_CR_OFF) |= TWI_CR_STOP;
110 * The start is not performed when we call the start function
111 * because the hardware should know the first data byte to send.
112 * Generally to perform a byte send we should write the slave address
113 * in slave address register and the first byte to send in data registry.
114 * After then we can perform the start write procedure, and send really
115 * the our data. To use common bertos i2c api the really start will be
116 * performed when the user "put" or "send" its data. These tricks are hide
117 * from the driver implementation.
119 static void i2c_sam3_start(struct I2c *i2c, uint16_t slave_addr)
121 i2c->hw->first_xtranf = true;
123 if (I2C_TEST_START(i2c->flags) == I2C_START_R)
124 HWREG(i2c->hw->base + TWI_MMR_OFF) = TWI_MMR_DADR(slave_addr) | TWI_MMR_MREAD;
126 HWREG(i2c->hw->base + TWI_MMR_OFF) = TWI_MMR_DADR(slave_addr);
129 static void i2c_sam3_putc(I2c *i2c, const uint8_t data)
131 if (!waitTxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
133 LOG_ERR("i2c: txready timeout\n");
134 i2c->errors |= I2C_START_TIMEOUT;
138 HWREG(i2c->hw->base + TWI_THR_OFF) = data;
140 // On first byte sent wait for start timeout
141 if (i2c->hw->first_xtranf && !waitTxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
143 LOG_ERR("i2c: write start timeout\n");
144 i2c->errors |= I2C_START_TIMEOUT;
146 waitXferComplete(i2c);
149 i2c->hw->first_xtranf = false;
151 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
154 waitXferComplete(i2c);
158 static uint8_t i2c_sam3_getc(I2c *i2c)
160 if (i2c->hw->first_xtranf)
162 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_START;
163 i2c->hw->first_xtranf = false;
166 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
169 if (!waitRxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
171 LOG_ERR("i2c: read start timeout\n");
172 i2c->errors |= I2C_START_TIMEOUT;
176 return HWREG(i2c->hw->base + TWI_RHR_OFF);
179 static void i2c_setClock(I2c *i2c, int clock)
186 cl_div = ((CPU_FREQ / (2 * clock)) - 4) / (1 << ck_div);
195 LOG_INFO("i2c: using CKDIV = %lu and CLDIV/CHDIV = %lu\n\n", ck_div, cl_div);
197 HWREG(i2c->hw->base + TWI_CWGR_OFF) = 0;
198 HWREG(i2c->hw->base + TWI_CWGR_OFF) = (ck_div << 16) | (cl_div << 8) | cl_div;
202 static const I2cVT i2c_sam3_vt =
204 .start = i2c_sam3_start,
205 .getc = i2c_sam3_getc,
206 .putc = i2c_sam3_putc,
207 .write = i2c_genericWrite,
208 .read = i2c_genericRead,
211 struct I2cHardware i2c_sam3_hw[I2C_CNT];
215 * Initialize I2C module.
217 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
221 ASSERT(dev < I2C_CNT);
223 i2c->hw = &i2c_sam3_hw[dev];
224 i2c->vt = &i2c_sam3_vt;
226 // Configure I/O pins
227 pmc_periphEnable(PIOA_ID);
232 i2c->hw->base = TWI0_BASE;
233 PIO_PERIPH_SEL(TWI0_PORT, BV(TWI0_TWD) | BV(TWI0_TWCK), TWI0_PERIPH);
234 HWREG(TWI0_PORT + PIO_PDR_OFF) = BV(TWI0_TWD) | BV(TWI0_TWCK);
235 pmc_periphEnable(TWI0_ID);
238 i2c->hw->base = TWI1_BASE;
239 PIO_PERIPH_SEL(TWI1_PORT, BV(TWI1_TWD) | BV(TWI1_TWCK), TWI1_PERIPH);
240 HWREG(TWI1_PORT + PIO_PDR_OFF) = BV(TWI1_TWD) | BV(TWI1_TWCK);
241 pmc_periphEnable(TWI1_ID);
244 ASSERT(!"i2c: invalid dev number");
249 * Reset sequence: enable slave mode, reset, read RHR,
250 * disable slave and master modes.
252 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SVEN;
253 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SWRST;
254 dummy = HWREG(i2c->hw->base + TWI_RHR_OFF);
255 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SVDIS;
256 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_MSDIS;
259 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_MSEN;
261 i2c_setClock(i2c, clock);