4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32F103xx I2C driver.
35 * \author Daniele Basile <asterix@develer.com>
38 #include "cfg/cfg_i2c.h"
40 #define LOG_LEVEL I2C_LOG_LEVEL
41 #define LOG_FORMAT I2C_LOG_FORMAT
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
48 #include <cpu/power.h>
49 #include <drv/gpio_stm32.h>
50 #include <drv/irq_cm3.h>
51 #include <drv/clock_stm32.h>
53 #include <drv/timer.h>
60 struct stm32_i2c *base;
67 #define WAIT_BTF(base) \
69 while (!(base->SR1 & BV(SR1_BTF))) \
73 #define WAIT_RXNE(base) \
75 while (!(base->SR1 & BV(SR1_RXNE))) \
79 INLINE uint32_t get_status(struct stm32_i2c *base)
81 return ((base->SR1 | (base->SR2 << 16)) & 0x00FFFFFF);
85 * This fuction read the status registers of the i2c device
86 * and waint until the selec event happen. If occur one error
87 * the funtions return false.
89 INLINE bool wait_event(I2c *i2c, uint32_t event)
93 uint32_t stat = get_status(i2c->hw->base);
98 if (stat & SR1_ERR_MASK)
100 i2c->hw->base->SR1 &= ~SR1_ERR_MASK;
109 INLINE void start_w(struct I2c *i2c, uint16_t slave_addr)
112 * Loop on the select write sequence: when the eeprom is busy
113 * writing previously sent data it will reply to the SLA_W
114 * control byte with a NACK. In this case, we must
115 * keep trying until the eeprom responds with an ACK.
117 ticks_t start = timer_clock();
120 i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_START_SET;
122 if(!wait_event(i2c, I2C_EVENT_MASTER_MODE_SELECT))
124 LOG_ERR("ARBIT lost\n");
125 i2c->errors |= I2C_ARB_LOST;
129 i2c->hw->base->DR = slave_addr & OAR1_ADD0_RESET;
131 if(wait_event(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
134 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
136 LOG_ERR("Timeout on I2C START\n");
137 i2c->errors |= I2C_START_TIMEOUT;
138 i2c->hw->base->CR1 |= CR1_STOP_SET;
144 INLINE bool start_and_addr(struct I2c *i2c, uint16_t slave_addr)
146 i2c->hw->base->CR1 |= CR1_START_SET;
147 if(!wait_event(i2c, I2C_EVENT_MASTER_MODE_SELECT))
149 LOG_ERR("ARBIT lost\n");
150 i2c->errors |= I2C_ARB_LOST;
151 i2c->hw->base->CR1 |= CR1_STOP_SET;
155 i2c->hw->base->DR = (slave_addr | OAR1_ADD0_SET);
157 if (i2c->xfer_size == 2)
158 i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_POS_SET;
160 if(!wait_event(i2c, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
162 LOG_ERR("SLAR NACK:%08lx\n", get_status(i2c->hw->base));
163 i2c->errors |= I2C_NO_ACK;
164 i2c->hw->base->CR1 |= CR1_STOP_SET;
171 INLINE void start_r(struct I2c *i2c, uint16_t slave_addr)
173 if (!start_and_addr(i2c, slave_addr))
176 * Due to the hardware receive bytes from slave in automatically mode
177 * we should manage contextually all cases that we want to read one, two or more
178 * than two bytes. To comply this behaviour to our api we shoul bufferd some byte
179 * to hide all special case that needs to use this device.
181 if (i2c->xfer_size == 1)
183 i2c->hw->base->CR1 &= CR1_ACK_RESET;
187 IRQ_SAVE_DISABLE(irq);
188 (void)i2c->hw->base->SR2;
189 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
190 i2c->hw->base->CR1 |= CR1_STOP_SET;
193 WAIT_RXNE(i2c->hw->base);
195 i2c->hw->cache[0] = i2c->hw->base->DR;
196 i2c->hw->cached = true;
198 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
199 while (i2c->hw->base->CR1 & CR1_STOP_SET);
201 i2c->hw->base->CR1 |= CR1_ACK_SET;
203 else if (i2c->xfer_size == 2)
207 IRQ_SAVE_DISABLE(irq);
208 (void)i2c->hw->base->SR2;
209 i2c->hw->base->CR1 &= CR1_ACK_RESET;
212 WAIT_BTF(i2c->hw->base);
214 IRQ_SAVE_DISABLE(irq);
215 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
216 i2c->hw->base->CR1 |= CR1_STOP_SET;
218 * We store read bytes like a fifo..
220 i2c->hw->cache[1] = i2c->hw->base->DR;
221 i2c->hw->cache[0] = i2c->hw->base->DR;
222 i2c->hw->cached = true;
225 i2c->hw->base->CR1 &= CR1_POS_RESET;
226 i2c->hw->base->CR1 |= CR1_ACK_SET;
230 static void i2c_stm32_start(struct I2c *i2c, uint16_t slave_addr)
232 i2c->hw->cached = false;
234 if (I2C_TEST_START(i2c->flags) == I2C_START_W)
235 start_w(i2c, slave_addr);
236 else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
237 start_r(i2c, slave_addr);
240 static void i2c_stm32_putc(I2c *i2c, const uint8_t data)
242 i2c->hw->base->DR = data;
244 WAIT_BTF(i2c->hw->base);
246 /* Generate the stop if we finish to send all programmed bytes */
247 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
249 wait_event(i2c, I2C_EVENT_MASTER_BYTE_TRANSMITTED);
250 i2c->hw->base->CR1 |= CR1_STOP_SET;
254 static uint8_t i2c_stm32_getc(I2c *i2c)
258 ASSERT(i2c->xfer_size <= 2);
259 return i2c->hw->cache[i2c->xfer_size - 1];
263 WAIT_BTF(i2c->hw->base);
265 if (i2c->xfer_size == 3)
267 i2c->hw->base->CR1 &= CR1_ACK_RESET;
270 IRQ_SAVE_DISABLE(irq);
272 uint8_t data = i2c->hw->base->DR;
274 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
275 i2c->hw->base->CR1 |= CR1_STOP_SET;
277 i2c->hw->cache[1] = i2c->hw->base->DR;
281 WAIT_RXNE(i2c->hw->base);
283 i2c->hw->cache[0] = i2c->hw->base->DR;
284 i2c->hw->cached = true;
286 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
287 while (i2c->hw->base->CR1 & CR1_STOP_SET);
292 return i2c->hw->base->DR;
297 static const I2cVT i2c_stm32_vt =
299 .start = i2c_stm32_start,
300 .getc = i2c_stm32_getc,
301 .putc = i2c_stm32_putc,
302 .write = i2c_genericWrite,
303 .read = i2c_genericRead,
306 static struct I2cHardware i2c_stm32_hw[] =
309 .base = (struct stm32_i2c *)I2C1_BASE,
310 .clk_i2c_en = RCC_APB1_I2C1,
311 .pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
314 .base = (struct stm32_i2c *)I2C2_BASE,
315 .clk_i2c_en = RCC_APB1_I2C2,
316 .pin_mask = (GPIO_I2C2_SCL_PIN | GPIO_I2C2_SDA_PIN),
321 * Initialize I2C module.
323 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
326 i2c->hw = &i2c_stm32_hw[dev];
327 i2c->vt = &i2c_stm32_vt;
329 RCC->APB2ENR |= RCC_APB2_GPIOB;
330 RCC->APB1ENR |= i2c->hw->clk_i2c_en;
332 /* Set gpio to use I2C driver */
333 stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, i2c->hw->pin_mask,
334 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
336 /* Clear all needed registers */
337 i2c->hw->base->CR1 = 0;
338 i2c->hw->base->CR2 = 0;
339 i2c->hw->base->CCR = 0;
340 i2c->hw->base->TRISE = 0;
341 i2c->hw->base->OAR1 = 0;
343 /* Set PCLK1 frequency accornding to the master clock settings. See stm32_clock.c */
344 i2c->hw->base->CR2 |= CR2_FREQ_36MHZ;
346 /* Configure spi in standard mode */
347 ASSERT2(clock >= 100000, "fast mode not supported");
349 i2c->hw->base->CCR |= (uint16_t)((CR2_FREQ_36MHZ * 1000000) / (clock << 1));
350 i2c->hw->base->TRISE |= (CR2_FREQ_36MHZ + 1);
352 i2c->hw->base->CR1 |= CR1_PE_SET;